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2 tccr1b - timer/counter1 control register b, Atmega128rfa1 – Rainbow Electronics ATmega128RFA1 User Manual

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8266A-MCU Wireless-12/09

ATmega128RFA1

Register Bits

Value

Description

0x2

PWM, phase correct, 9-bit

0x3

PWM, phase correct, 10-bit

0x4

CTC, TOP = OCRnA

0x5

Fast PWM, 8-bit

0x6

Fast PWM, 9-bit

0x7

Fast PWM, 10-bit

0x8

PWM, Phase and frequency correct, TOP =
ICRn

0x9

PWM, Phase and frequency correct, TOP =
OCRnA

0xA

PWM, Phase correct, TOP = ICRn

0xB

PWM, Phase correct, TOP = OCRnA

0xC

CTC, TOP = OCRnA

0xD

Reserved

0xE

Fast PWM, TOP = ICRn

0xF

Fast PWM, TOP = OCRnA

18.11.2 TCCR1B – Timer/Counter1 Control Register B

Bit

7

6

5

4

3

2

1

0

NA ($81)

ICNC1

ICES1

Res

WGM13 WGM12

CS12

CS11

CS10

TCCR1B

Read/Write

RW

RW

R

RW

RW

RW

RW

RW

Initial Value

0

0

0

0

0

0

0

0

Bit 7 – ICNC1 - Input Capture 1 Noise Canceller

Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise
Canceler is activated, the input from the Input Capture Pin (ICP1) is filtered. The filter
function requires four successive equal valued samples of the ICP1 pin for changing its
output. The input capture is therefore delayed by four Oscillator cycles when the noise
canceler is enabled.

Bit 6 – ICES1 - Input Capture 1 Edge Select

This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a
capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used
as trigger. When the ICES1 bit is written to one, a rising (positive) edge will trigger the
capture. When a capture is triggered according to the ICES1 setting, the counter value
is copied into the Input Capture Register (ICR1). The event will also set the Input
Capture Flag (ICF1). This can be used to cause an Input Capture Interrupt, if this
interrupt is enabled. When the ICR1 is used as TOP value (see description of the
WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is
disconnected and consequently the input capture function is disabled.

Bit 5 – Res - Reserved Bit

This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.

Bit 4:3 – WGM11:10 - Waveform Generation Mode