6 reset state, 3 interrupt handling, Atmega128rfa1 – Rainbow Electronics ATmega128RFA1 User Manual
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8266A-MCU Wireless-12/09
ATmega128RFA1
During the transition to BUSY_TX state, the PLL frequency shifts to the transmit
frequency. The actual transmission of the first data chip of the SHR starts after 16 µs to
allow PLL settling and PA ramp-up, see
. After transmission of
the SHR, the Frame Buffer content is transmitted. In case the PHR indicates a frame
length of zero, the transmission is aborted.
After the frame transmission has completed, the radio transceiver automatically turns
off the power amplifier, generates a TRX24_TX_END interrupt and returns into PLL_ON
state.
9.4.1.2.6 RESET State
The RESET state is used to set back the state machine and to reset all registers of the
radio transceiver to their default values.
A reset forces the radio transceiver into the TRX_OFF state.
A reset is initiated by a ATmega128RFA1 main reset (see
) or a radio transceiver reset (see
"Transceiver Pin Register TRXPR" on page 32
).
During radio transceiver reset the TRXPR register is not cleared and therefore the
application software has to set the SLPTR bit to “0”.
9.4.1.3 Interrupt Handling
All interrupts provided by the radio transceiver are supported in Basic Operating Mode
(see
).
Required interrupts must be enabled by writing to register IRQ_MASK and the global
interrupt enable flag must be set. For a general explanation of the interrupt handling
refer to
"Reset and Interrupt Handling" on page 15
.
For example, interrupts are provided to observe the status of the RX and TX operations.
On receive the TRX24_RX_START interrupt indicates the detection of a valid PHR, the
TRX24_XAH_AMI interrupt an address match and the TRX24_RX_END interrupt the
completion of the frame reception.
On transmit the TRX24_TX_END interrupt indicates the completion of the frame
transmission.
shows an example for a transmit/receive transaction between
two devices and the related interrupt events in Basic Operating Mode. Device 1
transmits a frame containing a MAC header (in this example of length 7), payload and
valid FCS. The frame is received by Device 2 which generates the interrupts during the
processing of the incoming frame. The received frame is stored in the Frame Buffer.
If the received frame passes the address filter (refer to section
) an address match TRX24_XAH_AMI interrupt is issued after the reception of
the MAC header (MHR).
In Basic Operating Mode the TRX24_RX_END interrupt is issued at the end of the
received frame. In Extended Operating Mode (refer to
) the interrupt is only issued if the received frame passes the address filter and
the FCS is valid. Further exceptions are explained in
.
Processing delay t
IRQ
is a typical value (see chapter
).