Rainbow Electronics ATmega128RFA1 Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for ATmega128RFA1 Rainbow Electronics
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 524 |
| Size: | 4.54 MB |
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Document Outline
- 1 Pin Configurations
- 2 Disclaimer
- 3 Overview
- 3.1 Block Diagram
- 3.2 Pin Descriptions
- 3.2.1 EVDD
- 3.2.2 DEVDD
- 3.2.3 AVDD
- 3.2.4 DVDD
- 3.2.5 DVSS
- 3.2.6 AVSS
- 3.2.7 Port B (PB7...PB0)
- 3.2.8 Port D (PD7...PD0)
- 3.2.9 Port E (PE7...PE0)
- 3.2.10 Port F (PF7...PF0)
- 3.2.11 Port G (PG5 PG0)
- 3.2.12 AVSS_RFP
- 3.2.13 AVSS_RFN
- 3.2.14 RFP
- 3.2.15 RFN
- 3.2.16 RSTN
- 3.2.17 RSTON
- 3.2.18 XTAL1
- 3.2.19 XTAL2
- 3.2.20 AREF
- 3.2.21 TST
- 3.2.22 CLKI
- 3.3 Compatibility to ATmega1281/2561
- 4 Resources
- 5 About Code Examples
- 6 Data Retention
- 7 AVR CPU Core
- 8 AVR Memories
- 9 Low-Power 2.4 GHz Transceiver
- 9.1 Features
- 9.2 General Circuit Description
- 9.3 Transceiver to Microcontroller Interface
- 9.4 Operating Modes
- 9.4.1 Basic Operating Mode
- 9.4.2 Extended Operating Mode
- 9.4.2.1 State Control
- 9.4.2.2 Configuration
- 9.4.2.3 RX_AACK_ON - Receive with Automatic ACK
- 9.4.2.3.1 Description of RX_AACK Configuration Bits
- 9.4.2.3.2 Configuration of IEEE Scenarios
- 9.4.2.3.3 Configuration of non IEEE 802.15.4 Compliant Scenarios
- 9.4.2.4 Frame Filtering
- 9.4.2.5 TX_ARET_ON - Transmit with Automatic Retry and CSMA-CA Retry
- 9.4.2.6 Interrupt Handling
- 9.4.2.7 Register Summary
- 9.5 Functional Description
- 9.5.1 Introduction - IEEE 802.15.4-2006 Frame Format
- 9.5.1.1 PHY Protocol Layer Data Unit (PPDU)
- 9.5.1.2 MAC Protocol Layer Data Unit (MPDU)
- 9.5.1.2.1 MAC Header (MHR) Fields
- 9.5.1.2.2 Frame Control Field (FCF)
- 9.5.1.2.3 Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006
- 9.5.1.2.4 Sequence Number
- 9.5.1.2.5 Addressing Fields
- 9.5.1.2.6 Auxiliary Security Header Field
- 9.5.1.2.7 MAC Service Data Unit (MSDU)
- 9.5.1.2.8 MAC Footer (MFR) Fields
- 9.5.2 Frame Check Sequence (FCS)
- 9.5.3 Received Signal Strength Indicator (RSSI)
- 9.5.4 Energy Detection (ED)
- 9.5.5 Clear Channel Assessment (CCA)
- 9.5.6 Link Quality Indication (LQI)
- 9.5.1 Introduction - IEEE 802.15.4-2006 Frame Format
- 9.6 Module Description
- 9.7 Radio Transceiver Usage
- 9.8 Radio Transceiver Extended Feature Set
- 9.9 Continuous Transmission Test Mode
- 9.10 Abbreviations
- 9.11 Reference Documents
- 9.12 Register Description
- 9.12.1 AES_CTRL - AES Control Register
- 9.12.2 AES_STATUS - AES Status Register
- 9.12.3 AES_STATE - AES Plain and Cipher Text Buffer Register
- 9.12.4 AES_KEY - AES Encryption and Decryption Key Buffer Register
- 9.12.5 TRX_STATUS - Transceiver Status Register
- 9.12.6 TRX_STATE - Transceiver State Control Register
- 9.12.7 TRX_CTRL_0 - Reserved
- 9.12.8 TRX_CTRL_1 - Transceiver Control Register 1
- 9.12.9 PHY_TX_PWR - Transceiver Transmit Power Control Register
- 9.12.10 PHY_RSSI - Receiver Signal Strength Indicator Register
- 9.12.11 PHY_ED_LEVEL - Transceiver Energy Detection Level Register
- 9.12.12 PHY_CC_CCA - Transceiver Clear Channel Assessment (CCA) Control Register
- 9.12.13 CCA_THRES - Transceiver CCA Threshold Setting Register
- 9.12.14 RX_CTRL - Transceiver Receive Control Register
- 9.12.15 SFD_VALUE - Start of Frame Delimiter Value Register
- 9.12.16 TRX_CTRL_2 - Transceiver Control Register 2
- 9.12.17 ANT_DIV - Antenna Diversity Control Register
- 9.12.18 IRQ_MASK - Transceiver Interrupt Enable Register
- 9.12.19 IRQ_STATUS - Transceiver Interrupt Status Register
- 9.12.20 VREG_CTRL - Voltage Regulator Control and Status Register
- 9.12.21 BATMON - Battery Monitor Control and Status Register
- 9.12.22 XOSC_CTRL - Crystal Oscillator Control Register
- 9.12.23 RX_SYN - Transceiver Receiver Sensitivity Control Register
- 9.12.24 XAH_CTRL_1 - Transceiver Acknowledgment Frame Control Register 1
- 9.12.25 FTN_CTRL - Transceiver Filter Tuning Control Register
- 9.12.26 PLL_CF - Transceiver Center Frequency Calibration Control Register
- 9.12.27 PLL_DCU - Transceiver Delay Cell Calibration Control Register
- 9.12.28 PART_NUM - Device Identification Register (Part Number)
- 9.12.29 VERSION_NUM - Device Identification Register (Version Number)
- 9.12.30 MAN_ID_0 - Device Identification Register (Manufacture ID Low Byte)
- 9.12.31 MAN_ID_1 - Device Identification Register (Manufacture ID High Byte)
- 9.12.32 SHORT_ADDR_0 - Transceiver MAC Short Address Register (Low Byte)
- 9.12.33 SHORT_ADDR_1 - Transceiver MAC Short Address Register (High Byte)
- 9.12.34 PAN_ID_0 - Transceiver Personal Area Network ID Register (Low Byte)
- 9.12.35 PAN_ID_1 - Transceiver Personal Area Network ID Register (High Byte)
- 9.12.36 IEEE_ADDR_0 - Transceiver MAC IEEE Address Register 0
- 9.12.37 IEEE_ADDR_1 - Transceiver MAC IEEE Address Register 1
- 9.12.38 IEEE_ADDR_2 - Transceiver MAC IEEE Address Register 2
- 9.12.39 IEEE_ADDR_3 - Transceiver MAC IEEE Address Register 3
- 9.12.40 IEEE_ADDR_4 - Transceiver MAC IEEE Address Register 4
- 9.12.41 IEEE_ADDR_5 - Transceiver MAC IEEE Address Register 5
- 9.12.42 IEEE_ADDR_6 - Transceiver MAC IEEE Address Register 6
- 9.12.43 IEEE_ADDR_7 - Transceiver MAC IEEE Address Register 7
- 9.12.44 XAH_CTRL_0 - Transceiver Extended Operating Mode Control Register
- 9.12.45 CSMA_SEED_0 - Transceiver CSMA-CA Random Number Generator Seed Register
- 9.12.46 CSMA_SEED_1 - Transceiver Acknowledgment Frame Control Register 2
- 9.12.47 CSMA_BE - Transceiver CSMA-CA Back-off Exponent Control Register
- 9.12.48 TST_CTRL_DIGI - Transceiver Digital Test Control Register
- 9.12.49 TST_RX_LENGTH - Transceiver Received Frame Length Register
- 9.12.50 TRXFBST - Start of frame buffer
- 9.12.51 TRXFBEND - End of frame buffer
- 10 MAC Symbol Counter
- 10.1 Main Features
- 10.2 Clock source selection and Sleep/Active mode operation
- 10.3 32 bit Register Access (Atomic Read/Write)
- 10.4 Symbol Counter (32 bit, SCCNT)
- 10.5 Symbol Counter SFD Timestamp Register (32 bit, SCTSR, Read Only)
- 10.6 Symbol Counter Beacon Timestamp Register (32 bit, SCBTSR)
- 10.7 Compare Unit (3x 32 bit, SCOCR1, SCOCR2, SCOCR3)
- 10.8 Interrupt Control Registers
- 10.9 Backoff Slot Counter
- 10.10 Symbol Counter Usage
- 10.11 Register Description
- 10.11.1 SCCNTHH - Symbol Counter Register HH-Byte
- 10.11.2 SCCNTHL - Symbol Counter Register HL-Byte
- 10.11.3 SCCNTLH - Symbol Counter Register LH-Byte
- 10.11.4 SCCNTLL - Symbol Counter Register LL-Byte
- 10.11.5 SCTSRHH - Symbol Counter Frame Timestamp Register HH-Byte
- 10.11.6 SCTSRHL - Symbol Counter Frame Timestamp Register HL-Byte
- 10.11.7 SCTSRLH - Symbol Counter Frame Timestamp Register LH-Byte
- 10.11.8 SCTSRLL - Symbol Counter Frame Timestamp Register LL-Byte
- 10.11.9 SCBTSRHH - Symbol Counter Beacon Timestamp Register HH-Byte
- 10.11.10 SCBTSRHL - Symbol Counter Beacon Timestamp Register HL-Byte
- 10.11.11 SCBTSRLH - Symbol Counter Beacon Timestamp Register LH-Byte
- 10.11.12 SCBTSRLL - Symbol Counter Beacon Timestamp Register LL-Byte
- 10.11.13 SCOCR1HH - Symbol Counter Output Compare Register 1 HH-Byte
- 10.11.14 SCOCR1HL - Symbol Counter Output Compare Register 1 HL-Byte
- 10.11.15 SCOCR1LH - Symbol Counter Output Compare Register 1 LH-Byte
- 10.11.16 SCOCR1LL - Symbol Counter Output Compare Register 1 LL-Byte
- 10.11.17 SCOCR2HH - Symbol Counter Output Compare Register 2 HH-Byte
- 10.11.18 SCOCR2HL - Symbol Counter Output Compare Register 2 HL-Byte
- 10.11.19 SCOCR2LH - Symbol Counter Output Compare Register 2 LH-Byte
- 10.11.20 SCOCR2LL - Symbol Counter Output Compare Register 2 LL-Byte
- 10.11.21 SCOCR3HH - Symbol Counter Output Compare Register 3 HH-Byte
- 10.11.22 SCOCR3HL - Symbol Counter Output Compare Register 3 HL-Byte
- 10.11.23 SCOCR3LH - Symbol Counter Output Compare Register 3 LH-Byte
- 10.11.24 SCOCR3LL - Symbol Counter Output Compare Register 3 LL-Byte
- 10.11.25 SCCR0 - Symbol Counter Control Register 0
- 10.11.26 SCCR1 - Symbol Counter Control Register 1
- 10.11.27 SCSR - Symbol Counter Status Register
- 10.11.28 SCIRQS - Symbol Counter Interrupt Status Register
- 10.11.29 SCIRQM - Symbol Counter Interrupt Mask Register
- 11 System Clock and Clock Options
- 11.1 Overview
- 11.2 Clock Systems and their Distribution
- 11.3 Clock Sources
- 11.4 Calibrated Internal RC Oscillator
- 11.5 128 kHz Internal Oscillator
- 11.6 External Clock
- 11.7 Transceiver Crystal Oscillator
- 11.8 Clock Output Buffer
- 11.9 Timer/Counter Oscillator
- 11.10 System Clock Prescaler
- 11.11 Register Description
- 12 Power Management and Sleep Modes
- 12.1 Deep-Sleep Mode
- 12.2 AVR Microcontroller Sleep Modes
- 12.3 Power Reduction Register
- 12.4 Minimizing Power Consumption
- 12.5 Supply Voltage and Leakage Control
- 12.6 Register Description
- 12.6.1 SMCR - Sleep Mode Control Register
- 12.6.2 PRR0 - Power Reduction Register0
- 12.6.3 PRR1 - Power Reduction Register 1
- 12.6.4 PRR2 - Power Reduction Register 2
- 12.6.5 TRXPR - Transceiver Pin Register
- 12.6.6 DRTRAM0 - Data Retention Configuration Register of SRAM 0
- 12.6.7 DRTRAM1 - Data Retention Configuration Register of SRAM 1
- 12.6.8 DRTRAM2 - Data Retention Configuration Register of SRAM 2
- 12.6.9 DRTRAM3 - Data Retention Configuration Register of SRAM 3
- 12.6.10 LLCR - Low Leakage Voltage Regulator Control Register
- 12.6.11 LLDRH - Low Leakage Voltage Regulator Data Register (High-Byte)
- 12.6.12 LLDRL - Low Leakage Voltage Regulator Data Register (Low-Byte)
- 12.6.13 DPDS0 - Port Driver Strength Register 0
- 12.6.14 DPDS1 - Port Driver Strength Register 1
- 13 System Control and Reset
- 14 I/O-Ports
- 14.1 Introduction
- 14.2 Ports as General Digital I/O
- 14.3 Alternate Port Functions
- 14.4 Register Description
- 14.4.1 MCUCR - MCU Control Register
- 14.4.2 DPDS0 - Port Driver Strength Register 0
- 14.4.3 DPDS1 - Port Driver Strength Register 1
- 14.4.4 PORTB - Port B Data Register
- 14.4.5 DDRB - Port B Data Direction Register
- 14.4.6 PINB - Port B Input Pins Address
- 14.4.7 PORTD - Port D Data Register
- 14.4.8 DDRD - Port D Data Direction Register
- 14.4.9 PIND - Port D Input Pins Address
- 14.4.10 PORTE - Port E Data Register
- 14.4.11 DDRE - Port E Data Direction Register
- 14.4.12 PINE - Port E Input Pins Address
- 14.4.13 PORTF - Port F Data Register
- 14.4.14 DDRF - Port F Data Direction Register
- 14.4.15 PINF - Port F Input Pins Address
- 14.4.16 PORTG - Port G Data Register
- 14.4.17 DDRG - Port G Data Direction Register
- 14.4.18 PING - Port G Input Pins Address
- 15 Interrupts
- 16 External Interrupts
- 16.1 Pin Change Interrupt Timing
- 16.2 Register Description
- 16.2.1 EICRA - External Interrupt Control Register A
- 16.2.2 EICRB - External Interrupt Control Register B
- 16.2.3 EIMSK - External Interrupt Mask Register
- 16.2.4 EIFR - External Interrupt Flag Register
- 16.2.5 PCICR - Pin Change Interrupt Control Register
- 16.2.6 PCIFR - Pin Change Interrupt Flag Register
- 16.2.7 PCMSK2 - Pin Change Mask Register 2
- 16.2.8 PCMSK1 - Pin Change Mask Register 1
- 16.2.9 PCMSK0 - Pin Change Mask Register 0
- 17 8-bit Timer/Counter0 with PWM
- 17.1 Features
- 17.2 Overview
- 17.3 Timer/Counter Clock Sources
- 17.4 Counter Unit
- 17.5 Output Compare Unit
- 17.6 Compare Match Output Unit
- 17.7 Modes of Operation
- 17.8 Timer/Counter Timing Diagrams
- 17.9 Register Description
- 17.9.1 GTCCR - General Timer/Counter Control Register
- 17.9.2 TCCR0A - Timer/Counter0 Control Register A
- 17.9.3 TCCR0B - Timer/Counter0 Control Register B
- 17.9.4 TCNT0 - Timer/Counter0 Register
- 17.9.5 OCR0A - Timer/Counter0 Output Compare Register
- 17.9.6 OCR0B - Timer/Counter0 Output Compare Register B
- 17.9.7 TIMSK0 - Timer/Counter0 Interrupt Mask Register
- 17.9.8 TIFR0 - Timer/Counter0 Interrupt Flag Register
- 18 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5)
- 18.1 Features
- 18.2 Overview
- 18.3 Accessing 16-bit Registers
- 18.4 Timer/Counter Clock Sources
- 18.5 Counter Unit
- 18.6 Input Capture Unit
- 18.7 Output Compare Units
- 18.8 Compare Match Output Unit
- 18.9 Modes of Operation
- 18.10 Timer/Counter Timing Diagrams
- 18.11 Register Description
- 18.11.1 TCCR1A - Timer/Counter1 Control Register A
- 18.11.2 TCCR1B - Timer/Counter1 Control Register B
- 18.11.3 TCCR1C - Timer/Counter1 Control Register C
- 18.11.4 TCNT1H - Timer/Counter1 High Byte
- 18.11.5 TCNT1L - Timer/Counter1 Low Byte
- 18.11.6 OCR1AH - Timer/Counter1 Output Compare Register A High Byte
- 18.11.7 OCR1AL - Timer/Counter1 Output Compare Register A Low Byte
- 18.11.8 OCR1BH - Timer/Counter1 Output Compare Register B High Byte
- 18.11.9 OCR1BL - Timer/Counter1 Output Compare Register B Low Byte
- 18.11.10 OCR1CH - Timer/Counter1 Output Compare Register C High Byte
- 18.11.11 OCR1CL - Timer/Counter1 Output Compare Register C Low Byte
- 18.11.12 ICR1H - Timer/Counter1 Input Capture Register High Byte
- 18.11.13 ICR1L - Timer/Counter1 Input Capture Register Low Byte
- 18.11.14 TIMSK1 - Timer/Counter1 Interrupt Mask Register
- 18.11.15 TIFR1 - Timer/Counter1 Interrupt Flag Register
- 18.11.16 TCCR3A - Timer/Counter3 Control Register A
- 18.11.17 TCCR3B - Timer/Counter3 Control Register B
- 18.11.18 TCCR3C - Timer/Counter3 Control Register C
- 18.11.19 TCNT3H - Timer/Counter3 High Byte
- 18.11.20 TCNT3L - Timer/Counter3 Low Byte
- 18.11.21 OCR3AH - Timer/Counter3 Output Compare Register A High Byte
- 18.11.22 OCR3AL - Timer/Counter3 Output Compare Register A Low Byte
- 18.11.23 OCR3BH - Timer/Counter3 Output Compare Register B High Byte
- 18.11.24 OCR3BL - Timer/Counter3 Output Compare Register B Low Byte
- 18.11.25 OCR3CH - Timer/Counter3 Output Compare Register C High Byte
- 18.11.26 OCR3CL - Timer/Counter3 Output Compare Register C Low Byte
- 18.11.27 ICR3H - Timer/Counter3 Input Capture Register High Byte
- 18.11.28 ICR3L - Timer/Counter3 Input Capture Register Low Byte
- 18.11.29 TIMSK3 - Timer/Counter3 Interrupt Mask Register
- 18.11.30 TIFR3 - Timer/Counter3 Interrupt Flag Register
- 18.11.31 TCCR4A - Timer/Counter4 Control Register A
- 18.11.32 TCCR4B - Timer/Counter4 Control Register B
- 18.11.33 TCCR4C - Timer/Counter4 Control Register C
- 18.11.34 TCNT4H - Timer/Counter4 High Byte
- 18.11.35 TCNT4L - Timer/Counter4 Low Byte
- 18.11.36 OCR4AH - Timer/Counter4 Output Compare Register A High Byte
- 18.11.37 OCR4AL - Timer/Counter4 Output Compare Register A Low Byte
- 18.11.38 OCR4BH - Timer/Counter4 Output Compare Register B High Byte
- 18.11.39 OCR4BL - Timer/Counter4 Output Compare Register B Low Byte
- 18.11.40 OCR4CH - Timer/Counter4 Output Compare Register C High Byte
- 18.11.41 OCR4CL - Timer/Counter4 Output Compare Register C Low Byte
- 18.11.42 ICR4H - Timer/Counter4 Input Capture Register High Byte
- 18.11.43 ICR4L - Timer/Counter4 Input Capture Register Low Byte
- 18.11.44 TIMSK4 - Timer/Counter4 Interrupt Mask Register
- 18.11.45 TIFR4 - Timer/Counter4 Interrupt Flag Register
- 18.11.46 TCCR5A - Timer/Counter5 Control Register A
- 18.11.47 TCCR5B - Timer/Counter5 Control Register B
- 18.11.48 TCCR5C - Timer/Counter5 Control Register C
- 18.11.49 TCNT5H - Timer/Counter5 High Byte
- 18.11.50 TCNT5L - Timer/Counter5 Low Byte
- 18.11.51 OCR5AH - Timer/Counter5 Output Compare Register A High Byte
- 18.11.52 OCR5AL - Timer/Counter5 Output Compare Register A Low Byte
- 18.11.53 OCR5BH - Timer/Counter5 Output Compare Register B High Byte
- 18.11.54 OCR5BL - Timer/Counter5 Output Compare Register B Low Byte
- 18.11.55 OCR5CH - Timer/Counter5 Output Compare Register C High Byte
- 18.11.56 OCR5CL - Timer/Counter5 Output Compare Register C Low Byte
- 18.11.57 ICR5H - Timer/Counter5 Input Capture Register High Byte
- 18.11.58 ICR5L - Timer/Counter5 Input Capture Register Low Byte
- 18.11.59 TIMSK5 - Timer/Counter5 Interrupt Mask Register
- 18.11.60 TIFR5 - Timer/Counter5 Interrupt Flag Register
- 19 Timer/Counter 0, 1, 3, 4, and 5 Prescaler
- 20 Output Compare Modulator (OCM1C0A)
- 21 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 21.1 Features
- 21.2 Overview
- 21.3 Timer/Counter Clock Sources
- 21.4 Counter Unit
- 21.5 Modes of Operation
- 21.6 Output Compare Unit
- 21.7 Compare Match Output Unit
- 21.8 Timer/Counter Timing Diagrams
- 21.9 Asynchronous Operation of Timer/Counter2
- 21.10 Timer/Counter Prescaler
- 21.11 Register Description
- 21.11.1 TIMSK2 - Timer/Counter Interrupt Mask register
- 21.11.2 TIFR2 - Timer/Counter Interrupt Flag Register
- 21.11.3 TCCR2A - Timer/Counter2 Control Register A
- 21.11.4 TCCR2B - Timer/Counter2 Control Register B
- 21.11.5 TCNT2 - Timer/Counter2
- 21.11.6 OCR2A - Timer/Counter2 Output Compare Register A
- 21.11.7 OCR2B - Timer/Counter2 Output Compare Register B
- 21.11.8 ASSR - Asynchronous Status Register
- 21.11.9 GTCCR - General Timer Counter Control register
- 22 SPI- Serial Peripheral Interface
- 23 USART
- 23.1 Features
- 23.2 Overview
- 23.3 Clock Generation
- 23.4 Frame Formats
- 23.5 USART Initialization
- 23.6 Data Transmission - The USART Transmitter
- 23.7 Data Reception - The USART Receiver
- 23.8 Asynchronous Data Reception
- 23.9 Multi-processor Communication Mode
- 23.10 Register Description
- 23.10.1 UDR0 - USART0 I/O Data Register
- 23.10.2 UCSR0A - USART0 Control and Status Register A
- 23.10.3 UCSR0B - USART0 Control and Status Register B
- 23.10.4 UCSR0C - USART0 Control and Status Register C
- 23.10.5 UBRR0H - USART0 Baud Rate Register High Byte
- 23.10.6 UBRR0L - USART0 Baud Rate Register Low Byte
- 23.10.7 UDR1 - USART1 I/O Data Register
- 23.10.8 UCSR1A - USART1 Control and Status Register A
- 23.10.9 UCSR1B - USART1 Control and Status Register B
- 23.10.10 UCSR1C - USART1 Control and Status Register C
- 23.10.11 UBRR1H - USART1 Baud Rate Register High Byte
- 23.10.12 UBRR1L - USART1 Baud Rate Register Low Byte
- 23.11 Examples of Baud Rate Setting
- 24 USART in SPI Mode
- 24.1 Overview
- 24.2 USART MSPIM vs. SPI
- 24.3 SPI Data Modes and Timing
- 24.4 Frame Formats
- 24.5 Data Transfer
- 24.6 USART MSPIM Register Description
- 24.6.1 UDRn - USART MSPIM I/O Data Register
- 24.6.2 UBRRnL and UBRRnH - USART MSPIM Baud Rate Registers
- 24.6.3 UCSR0A - USART0 MSPIM Control and Status Register A
- 24.6.4 UCSR0B - USART0 MSPIM Control and Status Register B
- 24.6.5 UCSR0C - USART0 MSPIM Control and Status Register C
- 24.6.6 UCSR1A - USART1 MSPIM Control and Status Register A
- 24.6.7 UCSR1B - USART1 MSPIM Control and Status Register B
- 24.6.8 UCSR1C - USART1 MSPIM Control and Status Register C
- 25 2-wire Serial Interface
- 26 AC - Analog Comparator
- 27 ADC - Analog to Digital Converter
- 27.1 Features
- 27.2 Operation
- 27.3 ADC Start-Up
- 27.4 Starting a Conversion
- 27.5 Pre-scaling and Conversion Timing
- 27.6 Changing Channel or Reference Selection
- 27.7 ADC Noise Canceller
- 27.8 ADC Conversion Result
- 27.9 Internal Temperature Measurement
- 27.10 SRAM DRT Voltage Measurement
- 27.11 Register Description
- 27.11.1 ADMUX - ADC Multiplexer Selection Register
- 27.11.2 ADCSRB - ADC Control and Status Register B
- 27.11.3 ADCSRA - ADC Control and Status Register A
- 27.11.4 ADCSRC - ADC Control and Status Register C
- 27.11.5 ADCL and ADCH - The ADC Data Register
- 27.11.6 DIDR0 - Digital Input Disable Register 0
- 27.11.7 DIDR2 - Digital Input Disable Register 2
- 27.11.8 BGCR - Reference Voltage Calibration Register
- 28 JTAG Interface and On-chip Debug System
- 29 IEEE 1149.1 (JTAG) Boundary-scan
- 30 Boot Loader Support - Read-While-Write Self-Programming
- 30.2 Application and Boot Loader Flash Sections
- 30.3 Read-While-Write and No Read-While-Write Flash Sections
- 30.4 Boot Loader Lock Bits
- 30.5 Addressing the Flash During Self-Programming
- 30.6 Self-Programming the Flash
- 30.6.1 Performing Page Erase by SPM
- 30.6.2 Filling the Temporary Buffer (Page Loading)
- 30.6.3 Performing a Page Write
- 30.6.4 Using the SPM Interrupt
- 30.6.5 Consideration While Updating BLS
- 30.6.6 Prevent Reading the RWW Section During Self-Programming
- 30.6.7 Setting the Boot Loader Lock Bits by SPM
- 30.6.8 EEPROM Write Prevents Writing to SPMCSR
- 30.6.9 Reading the Fuse and Lock Bits from Software
- 30.6.10 Reading the Signature Row from Software
- 30.6.11 Preventing Flash Corruption
- 30.6.12 Programming Time for Flash when Using SPM
- 30.6.13 Simple Assembly Code Example for a Boot Loader
- 30.6.14 Boot Loader Parameters for 128kByte of Flash Memory
- 30.7 Register Description
- 31 Memory Programming
- 31.1 Program And Data Memory Lock Bits
- 31.2 Fuse Bits
- 31.3 Signature Bytes
- 31.4 Calibration Byte
- 31.5 Page Size
- 31.6 Parallel Programming Parameters, Pin Mapping, and Commands
- 31.7 Parallel Programming
- 31.7.1 Enter Programming Mode
- 31.7.2 Considerations for Efficient Programming
- 31.7.3 Chip Erase
- 31.7.4 Programming the Flash
- 31.7.5 Programming the EEPROM
- 31.7.6 Reading the Flash
- 31.7.7 Reading the EEPROM
- 31.7.8 Programming the Fuse Low Bits
- 31.7.9 Programming the Fuse High Bits
- 31.7.10 Programming the Extended Fuse Bits
- 31.7.11 Programming the Lock Bits
- 31.7.12 Reading the Fuse and Lock Bits
- 31.7.13 Reading the Signature Bytes
- 31.7.14 Reading the Calibration Byte
- 31.7.15 Parallel Programming Characteristics
- 31.8 Serial Downloading
- 31.9 Programming via the JTAG Interface
- 31.9.1 Programming Specific JTAG Instructions
- 31.9.2 AVR_RESET (0xC)
- 31.9.3 PROG_ENABLE (0x4)
- 31.9.4 PROG_COMMANDS (0x5)
- 31.9.5 PROG_PAGELOAD (0x6)
- 31.9.6 PROG_PAGEREAD (0x7)
- 31.9.7 Data Registers
- 31.9.8 Reset Register
- 31.9.9 Programming Enable Register
- 31.9.10 Programming Command Register
- 31.9.11 Flash Data Byte Register
- 31.9.12 Programming Algorithm
- 31.9.13 Entering Programming Mode
- 31.9.14 Leaving Programming Mode
- 31.9.15 Performing Chip Erase
- 31.9.16 Programming the Flash
- 31.9.17 Reading the Flash
- 31.9.18 Programming the EEPROM
- 31.9.19 Reading the EEPROM
- 31.9.20 Programming the Fuses
- 31.9.21 Programming the Lock Bits
- 31.9.22 Reading the Fuses and Lock Bits
- 31.9.23 Reading the Signature Bytes
- 31.9.24 Reading the Calibration Byte
- 32 Application Circuits
- 33 Register Summary
- 34 Electrical Characteristics
- 35 Typical Characteristics
- 36 Ordering Information
- 37 Packaging Information
- 38 Errata
- 38.1 ATmega128RFA1 revision D (1.2)
- 38.2 ATmega128RFA1 revision C (1.1)
- 38.3 ATmega128RFA1 revision AB (1.0)
- 38.4 Compiler package WinAVR-20090313
- 38.5 Detailed errata description
- 38.5.1 Power-Chain turns off when power supply drops below 1.6V
- 38.5.2 JTAG interface reads wrong data
- 38.5.3 CSMA back-off calculation has reduced degree of randomness
- 38.5.4 Update of internal temporary registers for CSMA_SEED register may fail
- 38.5.5 Interrupt TRX24_CCA_ED_DONE may occur twice
- 38.5.6 DVREG_EXT bit is not write-protected
- 38.5.7 ENDRT bits have wrong reset value
- 39 Revision history
- Table of Contents