Rainbow Electronics ATmega128RFA1 - Manual (Page 319)

319
8266A-MCU Wireless-12/09
ATmega128RFA1
COM2x1 COM2x0 Description
1 0
Clear OC2x on Compare Match, set OC2x at BOTTOM, (non-
inverting mode).
1 1
Set OC2x on Compare Match, clear OC2x at BOTTOM, (inverting
mode).
Note: 1. A special case occurs when OCR2x equals TOP and COM2x1 is set. In this case,
the Compare Match is ignored, but the set or clear is done at BOTTOM. See "Fast
PWM Mode" on page 313 .
Table 17-4 shows the COM2x1:0 bit functionality when the WGM22:0 bits are set to
phase correct PWM mode.
Table 21-5. Compare Output Mode, Phase Correct PWM Mode
COM2x1 COM2x0 Description
0 0 Normal port operation, OC2x disconnected.
0 1
WGM22 = 0: Normal Port Operation, OC2A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
OC2B: not applicable, reserved function;
1 0
Clear OC2x on Compare Match when up-counting. Set OC2x on
Compare Match when down-counting.
1 1
Set OC2x on Compare Match when up-counting. Clear OC2x on
Compare Match when down-counting.
Note: 1. A special case occurs when OCR2x equals TOP and COM2x1 is set. In this case,
the Compare Match is ignored, but the set or clear is done at TOP. See "Phase
Correct PWM Mode" on page 314 for more details.
21.8 Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock
(clk
T2
) is therefore shown as a clock enable signal. In asynchronous mode, clk
I/O
should
be replaced by the Timer/Counter Oscillator clock. The figures include information on
when Interrupt Flags are set.
Figure 21-8 below contains timing data for basic
Timer/Counter operation. The figure shows the count sequence close to the MAX value
in all modes other than phase correct PWM mode.
Figure 21-8. Timer/Counter Timing Diagram, no Prescaling
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1