Rainbow Electronics ATmega128RFA1 - Manual (Page 336)

336
8266A-MCU Wireless-12/09
ATmega128RFA1
22.4 Register Description
22.4.1 SPCR – SPI Control Register
Bit 7 6 5 4 3 2 1 0
$2C ($4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – SPIE - SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set
and the if the Global Interrupt Enable bit in SREG is set.s
• Bit 6 – SPE - SPI Enable
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any
SPI operations.
• Bit 5 – DORD - Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR - Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when
written logic zero. If the Slave Select pin is configured as an input and is driven low
while MSTR is set, MSTR will be cleared and SPIF in SPSR are set. The user will then
have to set MSTR to re-enable SPI Master mode.
• Bit 3 – CPOL - Clock polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero,
SCK is low when idle. Refer to the "Data Modes" section for an example. The CPOL
functionality is summarized below.
Table 22-3 CPOL Register Bits
Register Bits Value Description
0 Rising (Leading Edge), Falling (Trailing
Edge) CPOL
1 Falling (Leading Egde), Rising (Trailing
Edge)
• Bit 2 – CPHA - Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading
(first) or trailing (last) edge of SCK. Refer to the "Data Modes" section for an example.
The CPOL functionality is summarized below.
Table 22-4 CPHA Register Bits
Register Bits Value Description
0 Sample (Leading Edge), Setup (Trailing
Edge) CPHA
1 Setup (Leading Edge), Sample (Trailing
Edge)
• Bit 1:0 – SPR1:0 - SPI Clock Rate Select 1 and 0