Rainbow Electronics ATmega128RFA1 User Manual
Page 189
189
8266A-MCU Wireless-12/09
ATmega128RFA1
Figure 14-3. Synchronization when reading an external applied pin value
Consider the clock period starting shortly after the first falling edge of the system clock.
The latch is closed when the clock is low, and goes transparent when the clock is high,
as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is
latched when the system clock goes low. It is clocked into the PINxn Register at the
succeeding positive clock edge. As indicated by the two arrows t
PD,MAX
and t
PD,MIN
, a
single signal transition on the pin will be delayed between ½ and 1½ system clock
period depending upon the time of assertion.
When reading back a software assigned pin value, a NOP instruction must be inserted
as indicated in
. The out instruction sets the “SYNC LATCH” signal at
the positive edge of the clock. In this case, the delay t
PD
through the synchronizer is 1
system clock period.
Figure 14-4. Synchronization when reading software assigned pin value
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low,
and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7.
The resulting pin values are read back again, but as previously discussed, a NOP
instruction is included to be able to read back the value recently assigned to some of
the pins.