Rainbow Electronics ATmega128RFA1 - Manual (Page 352)

352
8266A-MCU Wireless-12/09
ATmega128RFA1
C Code Example
(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRnA & (1<
}
Note: 1. See "About Code Examples" on page 7
23.8 Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling
asynchronous data reception. The clock recovery logic is used for synchronizing the
internally generated baud rate clock to the incoming asynchronous serial frames at the
RxDn pin. The data recovery logic samples and low pass filters each incoming bit,
thereby improving the noise immunity of the receiver. The asynchronous reception
operational range depends on the accuracy of the internal baud rate clock, the rate of
the incoming frames, and the frame size in number of bits.
23.8.1 Asynchronous Clock Recovery
The clock recovery logic synchronizes internal clock to the incoming serial frames.
Figure 23-5 below illustrates the sampling process of the start bit of an incoming frame.
The sample rate is 16 times the baud rate for Normal mode, and eight times the baud
rate for double speed mode. The horizontal arrows illustrate the synchronization
variation due to the sampling process. Note the larger time variation when using the
double speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done
when the RxDn line is idle (i.e., no communication activity).
Figure 23-5. Start Bit Sampling
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2
START IDLE
0 0
BIT 0
3
1 2 3 4 5 6 7 8 1 2 0
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn
line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-
sample as shown in the figure. The clock recovery logic then uses samples 8, 9 and 10
for Normal mode, and samples 4, 5 and 6 for double speed mode (indicated with
sample numbers inside boxes on the figure), to decide if a valid start bit is received. If
two or more of these three samples have logical high levels (the majority wins), the start
bit is rejected as a noise spike and the receiver starts looking for the next high to low-
transition. If however, a valid start bit is detected, the clock recovery logic is
synchronized and the data recovery can begin. The synchronization process is
repeated for each start bit.
23.8.2 Asynchronous Data Recovery
When the receiver clock is synchronized to the start bit, the data recovery can begin.
The data recovery unit uses a state machine that has 16 states for each bit in Normal
mode and eight states for each bit in double speed mode.
Figure 23-6 on page 353