Atmega128rfa1 – Rainbow Electronics ATmega128RFA1 User Manual
Page 171
171
8266A-MCU Wireless-12/09
ATmega128RFA1
12.6.8 DRTRAM2 – Data Retention Configuration Register of SRAM 2
Bit
7
6
5
4
3
2
1
0
NA ($133)
Resx7
Res
DRTSWOK ENDRT
Resx3
Resx2
Resx1
Resx0
DRTRAM2
Read/Write
RW
R
R
RW
RW
RW
RW
RW
Initial Value
0
0
0
0
0
0
0
0
The DRTRAM2 register controls the behavior of SRAM block 2 in the power-states
"power-save" and "power-down". To prevent any data loss the SRAM will not
completely disconnected from the power supply. Reserved bits will be overwritten
during chip reset by the factory calibration and should not be modified.
•
Bit 7 – Resx7 - Reserved
•
Bit 6 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
•
Bit 5 – DRTSWOK - DRT Switch OK
This bit indicates the status of the SRAM power-switch. A logical one indicates that the
SRAM supply voltage is fully available and the memory may be accessed normally.
•
Bit 4 – ENDRT - Enable SRAM Data Retention
During "Deep-Sleep" each SRAM block will either be switched off or provides data
retention of its memory content. This bit must set to one if data retention mode should
be used. Otherwise the SRAM is switched off (disconnected from the power supply)
and all its data are lost.
•
Bit 3:0 – Resx3:0 - Reserved
12.6.9 DRTRAM3 – Data Retention Configuration Register of SRAM 3
Bit
7
6
5
4
3
2
1
0
NA ($132)
Res1
Res0
DRTSWOK ENDRT
Resx3
Resx2
Resx1
Resx0
DRTRAM3
Read/Write
R
R
R
RW
RW
RW
RW
RW
Initial Value
0
0
0
0
0
0
0
0
The DRTRAM3 register controls the behavior of SRAM block 3 in the power-states
"power-save" and "power-down". To prevent any data loss the SRAM will not
completely disconnected from the power supply. Reserved bits will be overwritten
during chip reset by the factory calibration and should not be modified.
•
Bit 7:6 – Res1:0 - Reserved
•
Bit 5 – DRTSWOK - DRT Switch OK
This bit indicates the status of the SRAM power-switch. A logical one indicates that the
SRAM supply voltage is fully available and the memory may be accessed normally.
•
Bit 4 – ENDRT - Enable SRAM Data Retention
During "Deep-Sleep" each SRAM block will either be switched off or provides data
retention of its memory content. This bit must set to one if data retention mode should
be used. Otherwise the SRAM is switched off (disconnected from the power supply)
and all its data are lost.
•
Bit 3:0 – Resx3:0 - Reserved