9 bibliography, 10 on-chip debug related register in i/o memory, 1 ocdr - on-chip debug register – Rainbow Electronics ATmega128RFA1 User Manual
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8266A-MCU Wireless-12/09
ATmega128RFA1
The JTAG programming capability supports:
•
Flash programming and verifying.
•
EEPROM programming and verifying.
•
Fuse programming and verifying.
•
Lock bit programming and verifying.
The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or
LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a
chip erase. This is a security feature that ensures no back-door exists for reading out
the content of a secured device.
The details on programming through the JTAG interface and programming specific
JTAG instructions are given in the section
"Programming via the JTAG Interface" on
.
28.9 Bibliography
For more information about general Boundary-scan, the following literature can be
consulted:
•
IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan
Architecture, IEEE, 1993.
•
Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-
Wesley, 1992.
28.10 On-chip Debug Related Register in I/O Memory
28.10.1 OCDR – On-Chip Debug Register
Bit
7
6
5
4
3
2
1
0
$31 ($51)
OCDR7:0
OCDR
Read/Write
RW
RW
RW
RW
RW
RW
RW
RW
Initial Value
0
0
0
0
0
0
0
0
The OCDR Register provides a communication channel from the running program in
the microcontroller to the debugger. The CPU can transfer a byte to the debugger by
writing to this location. At the same time, an internal flag; I/O Debug Register Dirty
IDRD is set to indicate to the debugger that the register has been written. When the
CPU reads the OCDR Register the 7 LSB will be from the OCDR Register, while the
MSB is the IDRD bit. The debugger clears the IDRD bit when it has read the
information. In some AVR devices, this register is shared with a standard I/O location.
In this case, the OCDR Register can only be accessed if the OCDEN Fuse is
programmed, and the debugger enables access to the OCDR Register. In all other
cases, the standard I/O location is accessed.
•
Bit 7:0 – OCDR7:0 - On-Chip Debug Register Data
Table 28-16 OCDR Register Bits
Register Bits
Value
Description
OCDR7:0
0
Refer to the debugger documentation for
further information on how to use this
register.