Rainbow Electronics ATmega128RFA1 - Manual (Page 400)

400
8266A-MCU Wireless-12/09
ATmega128RFA1
3. The reading must be performed.
4. The transfer must be finished.
Note that data is transmitted both from Master to Slave and vice versa. The Master
must instruct the Slave what location it wants to read, requiring the use of the MT mode.
Subsequently, data must be read from the Slave, implying the use of the MR mode.
Thus, the transfer direction must be changed. The Master must keep control of the bus
during all these steps, and the steps should be carried out as an atomic operation. If
this principle is violated in a multi-master system, another Master can alter the data
pointer in the EEPROM between steps 2 and 3, and the Master will read the wrong data
location. Such a change in transfer direction is accomplished by transmitting a
REPEATED START between the transmission of the address byte and reception of the
data. After a REPEATED START, the Master keeps ownership of the bus. The following
figure shows the flow in this transfer.
Figure 25-19. Combining Several TWI Modes to Access a Serial EEPROM
Master Transmitter Master Receiver
S = START Rs = REPEATED START P = STOP
Transmitted from master to slave Transmitted from slave to master
S SLA+W A ADDRESS A Rs SLA+R A DATA A P
25.8 Multi-master Systems and Arbitration
If multiple masters are connected to the same bus, transmissions may be initiated
simultaneously by one or more of them. The TWI standard ensures that such situations
are handled in such a way that one of the masters will be allowed to proceed with the
transfer, and that no data will be lost in the process. An example of an arbitration
situation is depicted below, where two masters are trying to transmit data to a Slave
Receiver.
Figure 25-20. An Arbitration Example
Device 1
MASTER
TRANSMITTER
Device 2
MASTER
TRANSMITTER
Device 3
SLAVE
RECEIVER
Device n
SDA
SCL
........ R1 R2
DEVDD
Several different scenarios may arise during arbitration, as described below:
• Two or more masters are performing identical communication with the same Slave.
In this case, neither the Slave nor any of the masters will know about the bus
contention.
• Two or more masters are accessing the same Slave with different data or direction
bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data
bits. The masters trying to output a one on SDA while another Master outputs a zero