Rainbow Electronics ATmega128RFA1 - Manual (Page 298)

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8266A-MCU Wireless-12/09
ATmega128RFA1
The FOC5B bit is only active when the WGM53:0 bits specify a non-PWM mode. When
writing a logical one to the FOC5B bit, an immediate compare match is forced. Due to
the limited functionality of the Timer/Counter5 the match has no direct impact on any
output pin. Note that the FOC5B bits are implemented as strobes. Therefore it is the
value present in the COM5B1:0 bits that determine the effect of the forced compare. A
FOC5B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR5B as TOP. The FOC5B bits are always read
as zero.
• Bit 5 – FOC5C - Force Output Compare for Channel C
The FOC5C bit is only active when the WGM53:0 bits specify a non-PWM mode. When
writing a logical one to the FOC5C bit, an immediate compare match is forced. Due to
the limited functionality of the Timer/Counter5 the match has no direct impact on any
output pin. Note that the FOC5C bits are implemented as strobes. Therefore it is the
value present in the COM5C1:0 bits that determine the effect of the forced compare. A
FOC5C strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR5C as TOP. The FOC5C bits are always read
as zero.
• Bit 4:0 – Res4:0 - Reserved
These bits are reserved for future use.
18.11.49 TCNT5H – Timer/Counter5 High Byte
Bit 7 6 5 4 3 2 1 0
NA ($125) TCNT5H7:0 TCNT5H
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
The two Timer/Counter I/O locations (TCNT5H and TCNT5L, combined TCNT5) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying the
counter (TCNT5) while the counter is running introduces a risk of missing a compare
match between TCNT5 and one of the OCR5x Registers. Writing to the TCNT5
Register blocks (removes) the compare match on the following timer clock for all
compare units.
• Bit 7:0 – TCNT5H7:0 - Timer/Counter5 High Byte
18.11.50 TCNT5L – Timer/Counter5 Low Byte
Bit 7 6 5 4 3 2 1 0
NA ($124) TCNT5L7:0 TCNT5L
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
The two Timer/Counter I/O locations (TCNT5H and TCNT5L, combined TCNT5) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit