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2 serial programming algorithm, Atmega128rfa1 – Rainbow Electronics ATmega128RFA1 User Manual

Page 478

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478



8266A-MCU Wireless-12/09

ATmega128RFA1

Figure 31-13. Serial Programming and Verify

(1)(2)

Notes:

1. If the device is clocked by the internal Oscillator, it is not required to connect a

clock source to the CLKI pin.

2. V

DEVDD

-0.3V < V

EVDD

< V

DEVDD

+0.3V, both V

EVDD

and V

DEVDD

must stay in valid

supply voltage limits.

When programming the EEPROM, an auto-erase cycle is built into the self-timed
programming operation (in the Serial mode ONLY) and there is no need to first execute
the Chip Erase instruction. The Chip Erase operation turns the content of every memory
location in both the Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high
periods for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for f

ck

< 12 MHz, 3 CPU clock cycles for f

ck

>= 12 MHz;

High: > 2 CPU clock cycles for f

ck

< 12 MHz, 3 CPU clock cycles for f

ck

>= 12 MHz;

31.8.2 Serial Programming Algorithm

When writing serial data to the ATmega128RFA1, data is clocked on the rising edge of
SCK.

When reading data from the ATmega128RFA1, data is clocked on the falling edge of
SCK. See

Figure 31-15 on

page 481 for timing details.

To program and verify the ATmega128RFA1 in the serial programming mode, the
following sequence is recommended (See four byte instruction formats in

Table 31-17

on

page 479):

1. Power-up sequence: Apply power between DEVDD and DVSS while RSTN and

SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is
held low during power-up. In this case, RSTN must be given a positive pulse of at
least two CPU clock cycles duration after SCK has been set to “0”.

2. Wait for at least 20 ms and enable serial programming by sending the Programming

Enable serial instruction to pin PDI.

3. The serial programming instructions will not work if the communication is out of

synchronization. When in sync. the second byte (0x53), will echo back when issuing
the third byte of the Programming Enable instruction. Whether the echo is correct or