Rainbow Electronics ATmega128RFA1 - Manual (Page 157)

157
8266A-MCU Wireless-12/09
ATmega128RFA1
Active Clock Domains Oscillators Wake-up Sources
Power-down
X
(3)
X X X X
Power-save
X X
(2)
X
(3)
X X X X X
Standby (1)
X X (3) X X X X
Extended
Standby
X
(2)
X X
(2)
X
(3)
X X X X X
Notes: 1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT7:4, only level interrupt.
To enter any of the sleep modes, the SE bit in in the SMCR register (see "SMCR –
Sleep Mode Control Register" on page 166 ) must be written to logic one and a SLEEP
instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register
select which sleep mode will be activated by the SLEEP instruction. See chapter
"Register Description" on page 166 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up.
The MCU is then halted for four cycles in addition to the start-up time, executes the
interrupt routine, and resumes execution from the instruction following SLEEP. The
contents of the Register File and SRAM are unaltered when the device wakes up from
sleep. Note that SRAM data retention must be enabled in some sleep modes to
preserve the memory contents (see section
"SRAM with Data Retention" on page 163 ).
If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset
Vector.
12.2.1 Idle Mode
When the SM2:0 bits are written to 000 in the SMCR register, the SLEEP instruction
makes the MCU enter Idle mode, stopping the CPU but allowing the SPI, USART,
Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and the
interrupt system to continue operating. This sleep mode basically halts clk
CPU
and
clk
FLASH
, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as
internal ones like the Timer Overflow and USART Transmit Complete interrupts. If
wake-up from the Analog Comparator interrupt is not required, the Analog Comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and
Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC
is enabled, a conversion starts automatically when this mode is entered.
12.2.2 ADC Noise Reduction Mode
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter
ADC Noise Reduction mode (ADCNRM), stopping the CPU but allowing the ADC, the
external interrupts, 2-wire Serial Interface address match, Timer/Counter2 and the
Watchdog to continue operating (if enabled). This sleep mode basically halts clk
I/O
,
clk
CPU
, and clk
FLASH
, while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution
measurements. If the ADC is enabled, a conversion starts automatically when this
mode is entered. Apart form the ADC Conversion Complete interrupt, only an External
Reset, a Watchdog System Reset, a Watchdog interrupt, a Brown-out Reset, a 2-wire
serial interface interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt,