Rainbow Electronics ATmega128RFA1 - Manual (Page 263)

263
8266A-MCU Wireless-12/09
ATmega128RFA1
The PWM resolution for the phase and frequency correct PWM mode can be defined by
either ICRn or OCRnA. The minimum resolution allowed is 2 bit (ICRn or OCRnA set to
0x0003), and the maximum resolution is 16 bit (ICRn or OCRnA set to MAX). The PWM
resolution R
PFCPWM
in bits can be calculated with the following equation:
) 2 log(
) 1 log( +
=
TOP
R
PFCPWM
In phase and frequency correct PWM mode the counter is incremented until the counter
value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA
(WGMn3:0 = 9). The counter has then reached TOP and changes the count direction.
The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for
the phase correct and frequency correct PWM mode is shown in
Figure 18-9 below .
The figure shows phase and frequency correct PWM mode when OCRnA or ICRn is
used to define TOP. The TCNTn value is shown in the timing diagram as a histogram
for illustrating the dual-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare
matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a
compare match occurs.
Figure 18-9. Phase and Frequency Correct PWM Mode Timing Diagram
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
The Timer/Counter Overflow Flag (TOVn) is set at the timer clock cycle when the
OCRnx Registers are updated with the double-buffered value (at BOTTOM). The OCnA
or ICFn Flag is set after TCNTn has reached TOP when either OCRnA or ICRn is used
for defining the TOP value. The Interrupt Flags can then be used to generate an
interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is
higher or equal to the value of all of the Compare Registers. If the TOP value is lower
than any of the Compare Registers, a compare match will never occur between the
TCNTn and the OCRnx.
As Figure 18-9 shows the output generated is, in contrast to the phase correct mode,
symmetrical in all periods. Since the OCRnx Registers are updated at BOTTOM, the
length of the rising and the falling slopes will always be equal. This gives symmetrical
output pulses and is therefore frequency correct.