Rainbow Electronics ATmega128RFA1 - Manual (Page 233)

233
8266A-MCU Wireless-12/09
ATmega128RFA1
for the counter, hence also its resolution. This mode allows greater control of the
Compare Match output frequency. It also simplifies the operation of counting external
events.
The timing diagram for the CTC mode is shown in Figure 17-5. The counter value
(TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A. The
counter (TCNT0) is then cleared.
Figure 17-5. CTC Mode Timing Diagram
TCNTn
OCn
(Toggle)
OCnx Interrupt Flag Set
1 4 Period 2 3
(COMnx1:0 = 1)
An interrupt can be generated each time the counter value reaches the TOP value by
using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can
update the TOP value. However, changing TOP to a value close to BOTTOM when the
counter is running with no or a low prescaler value must be done with care since the
CTC mode does not have the double buffering feature. If the new value written to
OCR0A is lower than the current value of TCNT0, the counter will miss the Compare
Match. The counter will then have to count to its maximum value (0xFF) and wrap
around starting at 0x00 before the Compare Match can occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle
its logical level on each Compare Match by setting the Compare Output mode bits to
toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless
the data direction of the pin is set to output. The generated waveform will have a
maximum frequency of f
OC0
= f
clk_I/O
/2 when OCR0A is set to zero (0x00). The waveform
frequency is defined by the following equation:
) 0 1 ( 2
/ _
0
x OCR N
f
f
O I CLK
x OC
+ ⋅ ⋅
=
The N variable represents the prescale factor (1, 8, 64, 256 or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle
that the counter changes from MAX to 0x00.
17.7.3 Fast PWM Mode
The fast Pulse Width Modulation (PWM) mode (WGM02:0 = 3 or 7) provides a high
frequency PWM waveform generation option. The fast PWM mode differs from the
other PWM modes by its single-slope operation. The counter counts from BOTTOM to
TOP and then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and
OCR0A when WGM2:0 = 7. In non-inverting Compare Output mode the Output
Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x and
set at BOTTOM. In inverting Compare Output mode the output is set on Compare
Match and cleared at BOTTOM. Due to the single-slope operation, the operating
frequency of the fast PWM mode can be twice as high as in the phase correct PWM
mode that uses dual-slope operation. This high frequency operation makes the fast