Rainbow Electronics ATmega128RFA1 - Manual (Page 358)

358
8266A-MCU Wireless-12/09
ATmega128RFA1
Writing this bit to one enables interrupt on the UDRE0 Flag. A Data Register Empty
interrupt will be generated only if the UDRIE0 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the UDRE0 bit in UCSR0A is set.
• Bit 4 – RXEN0 - Receiver Enable
Writing this bit to one enables the USART Receiver. The Receiver will override normal
port operation for the RxD0 pin when enabled. Disabling the Receiver will flush the
receive buffer invalidating the FE0, DOR0 and UPE0 Flags.
• Bit 3 – TXEN0 - Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override
normal port operation for the TxD0 pin when enabled. The disabling of the Transmitter
(writing TXEN0 to zero) will not become effective until ongoing and pending
transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer
Register do not contain data to be transmitted. When disabled, the Transmitter will no
longer override the TxD0 port.
• Bit 2 – UCSZ02 - Character Size
The UCSZ02 bits combined with the UCSZ01:0 bit in UCSR0C sets the number of data
bits (Character Size) in the frame that the Receiver and Transmitter use.
• Bit 1 – RXB80 - Receive Data Bit 8
RXB80 is the 9th data bit of the received character when operating with serial frames
with nine data bits. The bit must be read before reading the lower 8 bits from UDR0.
• Bit 0 – TXB80 - Transmit Data Bit 8
TXB80 is the 9th data bit in the character to be transmitted when operating with serial
frames with nine data bits. The bit must be written before writing the lower 8 bits to
UDR0.
23.10.4 UCSR0C – USART0 Control and Status Register C
Bit 7 6 5 4 3 2 1 0
NA ($C2) UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 UCSR0C
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 1 0
• Bit 7:6 – UMSEL01:00 - USART Mode Select
These bits select the mode of operation of the USART0 as shown in the following table.
See section "USART in SPI Mode" for a full description of the Master SPI Mode
(MSPIM) operation.
Table 23-4 UMSEL0 Register Bits
Register Bits Value Description
0x00 Asynchronous USART
0x01 Synchronous USART
0x02 Reserved
UMSEL01:00
0x03 Master SPI (MSPIM)
• Bit 5:4 – UPM01:00 - Parity Mode
These bits enable and set type of parity generation and check. If enabled, the
Transmitter will automatically generate and send the parity of the transmitted data bits
within each frame. The Receiver will generate a parity value for the incoming data and