3 eimsk - external interrupt mask register, 4 eifr - external interrupt flag register, Atmega128rfa1 – Rainbow Electronics ATmega128RFA1 User Manual
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8266A-MCU Wireless-12/09
ATmega128RFA1
16.2.3 EIMSK – External Interrupt Mask Register
Bit
7
6
5
4
3
2
1
0
$1D ($3D)
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
EIMSK
Read/Write
RW
RW
RW
RW
RW
RW
RW
RW
Initial Value
0
0
0
0
0
0
0
0
When an INT7:0 bit is written to one and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control
bits in the External Interrupt Control Registers EICRA and EICRB define whether the
External Interrupt is activated on rising or falling edge or level sensed. Activity on any of
these pins will trigger an interrupt request even if the pin is enabled as an output. This
provides a way of generating a software interrupt.
•
Bit 7:0 – INT7:0 - External Interrupt Request Enable
Table 16-134 INT Register Bits
Register Bits
Value
Description
0x00
All external pin interrupts are disabled.
INT7:0
0xff
All external pin interrupts are enabled.
16.2.4 EIFR – External Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
$1C ($3C)
INTF7
INTF6
INTF5
INTF4
INTF3
INTF2
INTF1
INTF0
EIFR
Read/Write
RW
RW
RW
RW
RW
RW
RW
RW
Initial Value
0
0
0
0
0
0
0
0
When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0
becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit
INT7:0 in EIMSK are set (one), the MCU will jump to the interrupt vector. The flag is
cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by
writing a logical one to it. These flags are always cleared when INT7:0 are configured
as level interrupt. Note that when entering sleep mode with the INT3:0 interrupts
disabled, the input buffers on these pins will be disabled. This may cause a logic
change in internal signals which will set the INTF3:0 flags. See "Digital Input Enable
and Sleep Modes" for more information.
•
Bit 7:0 – INTF7:0 - External Interrupt Flag
Table 16-135 INTF Register Bits
Register Bits
Value
Description
0x00
No edge or logic change on INT7:0
occurred.
0x01
A edge or logic change on INT0 occurred
and triggered an interrupt request.
0x02
...
INTF7:0
0x80
A edge or logic change on INT7 occurred
and triggered an interrupt request.