Atmega128rfa1 – Rainbow Electronics ATmega128RFA1 User Manual
Page 162
162
8266A-MCU Wireless-12/09
ATmega128RFA1
6. SRAM block #3 (upper 4k bytes),
7. Radio transceiver including AES engine,
8. Non-volatile memory.
If the power-chain is completely enabled the standard AVR wake-up procedure
continues.
Figure 12-2 shows the chained startup procedure after power up. A module is only
switched on if it is not deselected by power reduction register (PRR1 or PRR2). This is
possible for SRAM blocks and radio transceiver power switch. At the end of the startup,
the pin RSTON is enabled.
Figure 12-3 shows a similar procedure, the startup from deep sleep.
For further timing information see
"Power Management Electrical Characteristics" on
.
Figure 12-2. Timing visualization of power up
startup
bandgap
startup
D V R E G
D R T sw itch
S R A M # 0
P O R
D R T sw itch
S R A M #1
D R T sw itch
S R A M #2
D R T sw itch
S R A M #3
pow er sw itch
radio trans.
pow er sw itch
N V M
oscillator
startup
t
P O R
t
B G
t
D V R E G
t
D R T_ O N
t
D R T_ O N
t
D R T_ O N
t
D R T_ O N
t
P W R S W _O N
t
P W R S W _O N
t
O S C _ S T A R T U P
R S T O N
t
S T A R T U P
Figure 12-3. Timing visualization of wakeup from deep sleep
startup
bandgap
startup
D V R E G
D R T sw itch
S R A M #0
S LEE P
D R T sw itch
S R AM #1
D R T sw itch
S R A M #2
D R T sw itch
S R A M #3
pow er sw itch
radio trans.
pow er sw itch
N V M
oscillator
startup
t
B G
t
D V R E G
t
D R T_ O N
t
D R T_O N
t
D R T _O N
t
D R T _O N
t
P W R S W _ O N
t
P W R S W _ O N
t
O S C _S T A R T U P
t
S T A R T U P
Sleep
Six sleep modes are defined for the CPU. Disabling the power-chain and thus switching
off of the above mentioned blocks makes only sense for the modes “power-down” and
“power-save”. Also an enabled radio transceiver prevents the power-chain from being
disabled.
In order to disable the power-chain, one of the following conditions must fit:
•
The radio transceiver has to be disabled (power reduction register PRR1 bit
PRTRX24).
•
The radio transceiver is sent into SLEEP mode (register TRXPR bit SLPTR).
The SRAM blocks may be configured separately to decrease their leakage current (see
section
page 163).
The following table shows the different implemented sleep modes and the behavior of
the power-chain depending on the current state of the radio transceiver.
Table 12-2. Power states of microcontroller and radio transceiver
AVR State
Radio Transceiver State
Powerchain
ON
ON
ON
ON
off (SLEEP or power reduction)
ON
off
(1…6)
ON
ON
off
(1,4…6)
off (SLEEP or power reduction)
ON