3 pll_on - pll state, 4 rx_on and busy_rx - rx listen and receive state, 5 busy_tx - transmit state – Rainbow Electronics ATmega128RFA1 User Manual
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8266A-MCU Wireless-12/09
ATmega128RFA1
9.4.1.2.3 PLL_ON – PLL State
Entering the PLL_ON state from TRX_OFF state first enables the analog voltage
regulator (AVREG). After the voltage regulator has been settled the PLL frequency
synthesizer is enabled. When the PLL has been settled at the receive frequency to a
channel defined by bits CHANNEL of register PHY_CC_CCA a successful PLL lock is
indicated by issuing a TRX24_PLL_LOCK interrupt.
If an RX_ON command is issued in PLL_ON state, the receiver is immediately enabled.
If the PLL has not been settled before the state change nevertheless takes place. Even
if the register bits TRX_STATUS of register TRX_STATUS indicates RX_ON, actual
frame reception can only start once the PLL has locked.
The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4.
9.4.1.2.4 RX_ON and BUSY_RX – RX Listen and Receive State
In RX_ON state the receiver blocks and the PLL frequency synthesizer are enabled.
The receive mode is internally separated into the RX_ON and BUSY_RX states. There
is no difference between these states with respect to the analog radio transceiver
circuitry, which are always turned on. In both states the receiver and the PLL frequency
synthesizer are enabled.
During RX_ON state the receiver listens for incoming frames. After detecting a valid
synchronization header (SHR), the receiver automatically enters the BUSY_RX state.
The reception of a valid PHY header (PHR) generates an TRX24_RX_START interrupt
and receives and demodulates the PSDU data.
During PSDU reception the frame data are stored continuously in the Frame Buffer until
the last byte was received. The completion of the frame reception is indicated by an
TRX24_RX_END interrupt and the radio transceiver reenters the state RX_ON. At the
same time the bits RX_CRC_VALID of register PHY_RSSI are updated with the result
of the FCS check (see
"Frame Check Sequence (FCS)" on page 66).
Received frames are passed to the frame filtering unit, refer to section
. If the content of the MAC addressing fields of a frame (refer to
IEEE 802.15.4 section 7.2.1) matches to the expected addresses, which is further
dependent on the addressing mode, an address match interrupt (TRX24_XAH_AMI) is
issued, refer to
. The expected address values are to be
stored in the registers Short-Address, PAN-ID and IEEE-address. Frame filtering is
available in Basic and Extended Operating Mode, refer to section
.
Leaving state RX_ON is only possible by writing a state change command to bits
TRX_CMD of register TRX_STATE.
9.4.1.2.5 BUSY_TX – Transmit State
A transmission can only be initiated in state PLL_ON. There are two ways to start a
transmission:
•
Setting Bit SLPTR of register TRXPR to ‘1’. The bit should be cleared before the
frame has been transmitted. This mode is for legacy operation and should be
replaced by the TX_START command below.
•
TX_START command to bits TRX_CMD of register TRX_STATE.
Either of these causes the radio transceiver into the BUSY_TX state.