Atmega128rfa1 – Rainbow Electronics ATmega128RFA1 User Manual
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8266A-MCU Wireless-12/09
ATmega128RFA1
2. At least one address field must be configured.
Address match, indicated by the TRX24_AMI interrupt is further controlled by the
content of subfields of the frame control field of a received frame according to the
following rule:
If (Destination Addressing Mode = 0 OR 1) AND (Source Addressing Mode = 0) no
TRX24_AMI interrupt is generated, refer to
.
This effectively
causes all acknowledgement frames not to be announced which otherwise always pass
the filter regardless of whether they are intended for this device or not.
For backward compatibility to IEEE 802.15.4-2003 third level filter rule 2 (Frame
Version) can be disabled by the bits AACK_FVN_MODE of register CSMA_SEED_1.
Frame filtering is available in Extended and Basic Operating Mode (see section
); a frame passing the frame filtering generates an
TRX24_AMI interrupt, if enabled.
Note:
1. Filter rule 1 is affected by register bits AACK_FLTR_RES_FT and
AACK_UPLD_RES_FT
(see
register
Acknowledgment Frame Control Register 1" on page 119
).
2. Filter rule 2 is affected by register bits AACK_FVN_MODE (see register
"CSMA_SEED_1 – Transceiver Acknowledgment Frame Control Register 2" on
page 129
).
9.4.2.4.1 RX_AACK Slotted Operation – Slotted Acknowledgement
The radio transceiver supports slotted acknowledgement operation according to
IEEE 802.15.4-2006, section 5.5.4.1.
In RX_AACK mode with bit SLOTTED_OPERATION of register XAH_CTRL_0 set, the
transmission of an acknowledgement frame has to be controlled by the microcontroller.
If an ACK frame has to be transmitted the radio transceiver expects writing SLPTR=1 to
actually start the transmission. This waiting state is signaled 6 symbol periods after the
reception of the last symbol of a data or MAC command frame by bits TRAC_STATUS
of register XAH_CTRL_0, which are set to SUCCESS_WAIT_FOR_ACK in that case. In
networks using slotted operation the start of the acknowledgment frame and thus the
exact timing must be provided by the microcontroller.
A timing example of an RX_AACK transaction with bit SLOTTED_OPERATION of
register XAH_CTRL_0 set is shown in the next figure. The acknowledgement frame is
ready to transmit 6 symbol times after the reception of the last symbol of a data or MAC
command frame. The transmission of the acknowledgement frame is initiated by the
microcontroller by writing SLPTR=1 and starts 16µs (t
TR10
) later. The interrupt latency
t
IRQ