Rainbow Electronics ATmega128RFA1 - Manual (Page 135)

135
8266A-MCU Wireless-12/09
ATmega128RFA1
It is also possible to manually set the register in order to provide a distinct starting value
for the relative compare modes (see next section).
10.7 Compare Unit (3x 32 bit, SCOCR1, SCOCR2, SCOCR3)
The compare unit contains 3 independent 32 bit compare modules and is used to
compare the current counter value with the value stored in the compare register, and
optionally the beacon timestamp register. There are two possible modes available
which can be selected separately for all three compare modules:
1. Absolute Compare: In this mode the value stored in the compare register is
compared directly with the symbol counter value (SCCNT == SCOCRx). If the values
are equal an interrupt is generated.
2. Relative Compare: This mode allows the compare between the current symbol
counter value and the compare value plus the beacon timestamp value (SCCNT ==
SCBTSR + SCOCRx). This mode can be used to generate an interrupt at a time offset
relative to the value stored in the beacon timestamp register.
Note that a beacon timestamp is valid after a valid FCS. The relative compare must
exceed the beacon length, otherwise no relative compare interrupt will occure.
10.8 Interrupt Control Registers
The interrupt status and mask registers control the interrupt generation. Each interrupt
can be enabled in SCIRQM (Symbol Counter IRQ Mask Register). If an interrupt
occurs, the appropriate interrupt flag within the interrupt status register is set regardless
of the interrupt mask register setting. If the appropriate interrupt is enabled, an interrupt
is generated.
The interrupt flags can be cleared either by:
1. Entering the respective interrupt handler, or
2. Writing “one” to the according interrupt flag in the interrupt status register.
All Interrupts can be used to wakeup the controller from any sleep state.
10.9 Backoff Slot Counter
The backoff slot counter can be used to provide accurate MAC protocol timing. The
counter is sourced by the transceiver clock and works only if the transceiver clock is
running. If the transceiver is disabled or in sleep mode the counter is also disabled.
The counter generates periodic Interrupts every 20 symbols, i.e. every 320 µs.
10.10 Symbol Counter Usage
10.10.1 SFD and Beacon Timestamp Generation
The SFD timestamp register is updated with the symbol counter value at the time the
SFD value has been received completely. For an incoming frame, the register is valid
after the RX_START IRQ was issued until the next RX_START IRQ. SFD timestamps
are generated for all incoming frames with valid SFD and length field even if the PSDU
is corrupted (invalid FCS).