8 timer/counter timing diagrams, Atmega128rfa1 – Rainbow Electronics ATmega128RFA1 User Manual
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8266A-MCU Wireless-12/09
ATmega128RFA1
In phase correct PWM mode, the compare unit allows generating PWM waveforms on
the OC0x pins. Setting the COM0x1:0 bits to 2 will produce a non-inverted PWM. An
inverted PWM output can be generated by setting the COM0x1:0 to 3. Setting the
COM0A0 bits to 1 allows the OC0A pin to toggle on Compare Matches if the WGM02
bit is set. This option is not available for the OC0B pin (see
).
The actual OC0x value will only be visible at the port pin if the data direction for the port
pin is set to output. The PWM waveform is generated by clearing (or setting) the OC0x
Register at the Compare Match between OCR0x and TCNT0 when the counter
increments, and by setting (or clearing) the OC0x Register at Compare Match between
OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output
f
OC0xPCPWM
when using phase-correct PWM can be calculated with the following
equation:
510
/
_
0
⋅
=
N
f
f
O
I
clk
xPCPWM
OC
The N variable represents the prescale factor (1, 8, 64, 256 or 1024).
The extreme values for the OCR0A Register represent special cases when generating
a PWM waveform output in the phase-correct PWM mode. If the OCR0A is set equal to
BOTTOM, the output will be continuously low and if set equal to MAX the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values.
At the very start of period 2 in Figure 17-7 OCnx has a transition from high to low even
though there is no Compare Match. The reason of this transition is to guarantee
symmetry around BOTTOM. There are two cases that give a transition without
Compare Match:
•
OCR0x changes its value from MAX like in
. When the
OCR0x value is MAX the OC0x pin value is the same as the result of a down-
counting Compare Match. To ensure symmetry around BOTTOM the OC0x value at
MAX must correspond to the result of an up-counting Compare Match.
•
The timer starts counting from a value higher than the one in OCR0x. For that
reason it misses the Compare Match and hence the OC0x change that would have
happened on the way up.
17.8 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T0
) is therefore
shown as a clock enable signal in the following figures. The figures include information
on when Interrupt Flags are set. Figure 17-8 contains timing data for basic
Timer/Counter operation. The figure shows the count sequence close to the MAX value
in all modes other than phase correct PWM mode.
Figure 17-8. Timer/Counter Timing Diagram, no Prescaling
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1