Rainbow Electronics ATmega128RFA1 - Manual (Page 250)

250
8266A-MCU Wireless-12/09
ATmega128RFA1
Clear Clear TCNTn (set all bits to zero);
clk
Tn
Timer/Counter clock;
TOP Signalize that TCNTn has reached maximum value;
BOTTOM Signalize that TCNTn has reached minimum value (zero);
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High
(TCNTnH) contains the upper eight bits of the counter and Counter Low (TCNTnL)
contains the lower eight bits. The TCNTnH Register can only be indirectly accessed by
the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU
accesses the high byte temporary register (TEMP). The temporary register is updated
with the TCNTnH value when the TCNTnL is read and TCNTnH is updated with the
temporary register value when TCNTnL is written. This allows the CPU to read or write
the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is
important to notice that there are special cases of writing to the TCNTn Register giving
unpredictable results when the counter is running. These special cases are described in
the sections of their importance.
Depending on the mode of operation, the counter is cleared, incremented or
decremented at each timer clock (clk
Tn
). The clk
Tn
can be generated from an external or
internal clock source selected by the Clock Select bits (CSn2:0). The timer is stopped
when no clock source is selected (CSn2:0 = 0). However, the TCNTn value can be
accessed by the CPU independent of whether clk
Tn
is present or not. A CPU write
overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the settings of the Waveform Generation
mode bits (WGMn3:0) located in the Timer/Counter Control Registers A and B
(TCCRnA and TCCRnB). There are close connections between how the counter
behaves (counts) and how waveforms are generated on the Output Compare outputs
OCnx. For more details about advanced counting sequences and waveform generation,
see
"Modes of Operation" on page 256 .
The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation
selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.
18.6 Input Capture Unit
The Timer/Counter incorporates an input capture unit that can capture external events
and give them a time-stamp indicating time of occurrence. The external signal indicating
an event, or multiple events, can be applied via the ICPn pin or alternatively, for the
Timer/Counter1 only, via the Analog Comparator unit. The time-stamps can then be
used to calculate frequency, duty-cycle and other features of the signal applied.
Alternatively the time-stamps can be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 18-3. The
elements of the block diagram not direct parts of the input capture unit are gray shaded.
The small “n” in register and bit names indicates the Timer/Counter number.
A capture will be triggered when a change of the logic level (an event) occurs on the
Input Capture Pin (ICPn), or alternatively on the analog Comparator output (ACO), and
this change matches the setting of the edge detector. When a capture is triggered, the
16-bit value of the counter (TCNTn) is written to the Input Capture Register (ICRn). The
Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is
copied into ICRn Register. If enabled (TICIEn = 1), the input capture flag generates an
input capture interrupt. The ICFn flag is automatically cleared when the interrupt is
executed. Alternatively the ICFn flag can be software-cleared by writing a logical one to
its I/O bit location.