Rainbow Electronics ATmega128RFA1 - Manual (Page 382)

382
8266A-MCU Wireless-12/09
ATmega128RFA1
must contain the same number of data packets, otherwise the result of the arbitration is
undefined.
Figure 25-8. Arbitration Between Two Masters
SDA from
Master A
SDA from
Master B
SDA Line
Synchronized
SCL Line
START
Master A Loses
Arbitration, SDA
A
SDA
25.5 Overview of the TWI Module
The TWI module is comprised of several sub-modules, as shown in Figure 25-9 below .
All registers drawn in a thick line are accessible through the AVR data bus.
Figure 25-9. Overview of the TWI Module
TWI Unit
Address Register
(TWAR)
Address Match Unit
Address Comparator
Control Unit
Control Register
(TWCR)
Status Register
(TWSR)
State Machine and
Status control
SCL
Slew-rate
Control
Spike
Filter
SDA
Slew-rate
Control
Spike
Filter
Bit Rate Generator
Bit Rate Register
(TWBR)
Prescaler
Bus Interface Unit
START / STOP
Control
Arbitration detection Ack
Spike Suppression
Address/Data Shift
Register (TWDR)