Rainbow Electronics ATmega128RFA1 - Manual (Page 100)

100
8266A-MCU Wireless-12/09
ATmega128RFA1
VCO - Voltage controlled oscillator
VREG - Voltage regulator
XOSC - Crystal oscillator
9.11 Reference Documents
[1] IEEE Std 802.15.4™-2006: Wireless Medium Access Control (MAC) and
Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area
Networks (LR-WPANs)
[2] IEEE Std 802.15.4™-2003: Wireless Medium Access Control (MAC) and
Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area
Networks (LR-WPANs)
[3] ANSI / ESD-STM5.1-2001: ESD Association Standard Test Method for
electrostatic discharge sensitivity testing – Human Body Model (HBM).
[4] ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic
discharge sensitivity testing – Charged Device Model (CDM).
[5] NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal
Information Processing Standards Publication 197, US Department of
Commerce/NIST, November 26, 2001
[6] ATmega128RFA1 Software Programming Model
9.12 Register Description
9.12.1 AES_CTRL – AES Control Register
Bit 7 6 5 4 3 2 1 0
NA ($13C) AES_REQUEST Res AES_MODE Res AES_DIR AES_IM Res1 Res0 AES_CTRL
Read/Write RW R RW R RW RW R R
Initial Value 0 0 0 0 0 0 0 0
This register controls the operation of the security module. Do not access this register
during AES operation to read the AES core status. A read or write access to the register
stops the ongoing processing. To read the AES status use bit AES_DONE of register
AES_STATUS. Note that the AES_CTRL register is cleared when entering the radio
transceiver SLEEP state.
• Bit 7 – AES_REQUEST - Request AES Operation.
A write access with AES_REQUEST = 1 initiates the AES operation.
• Bit 6 – Res - Reserved Bit
This bit is reserved for future use. The result of a read access is undefined. The register
bit must always be written with the reset value.
• Bit 5 – AES_MODE - Set AES Operation Mode
This register bit sets the AES operation mode (ECB/CBC Mode).