Rainbow Electronics ATmega128RFA1 - Manual (Page 289)

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8266A-MCU Wireless-12/09
ATmega128RFA1
Compare Match (CTC) mode using OCR4A as TOP. The FOC4A bits are always read
as zero.
• Bit 6 – FOC4B - Force Output Compare for Channel B
The FOC4B bit is only active when the WGM43:0 bits specify a non-PWM mode. When
writing a logical one to the FOC4B bit, an immediate compare match is forced. Due to
the limited functionality of the Timer/Counter4 the match has no direct impact on any
output pin. Note that the FOC4B bits are implemented as strobes. Therefore it is the
value present in the COM4B1:0 bits that determine the effect of the forced compare. A
FOC4B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR4B as TOP. The FOC4B bits are always read
as zero.
• Bit 5 – FOC4C - Force Output Compare for Channel C
The FOC4C bit is only active when the WGM43:0 bits specify a non-PWM mode. When
writing a logical one to the FOC4C bit, an immediate compare match is forced. Due to
the limited functionality of the Timer/Counter4 the match has no direct impact on any
output pin. Note that the FOC4C bits are implemented as strobes. Therefore it is the
value present in the COM4C1:0 bits that determine the effect of the forced compare. A
FOC4C strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR4C as TOP. The FOC4C bits are always read
as zero.
• Bit 4:0 – Res4:0 - Reserved
These bits are reserved for future use.
18.11.34 TCNT4H – Timer/Counter4 High Byte
Bit 7 6 5 4 3 2 1 0
NA ($A5) TCNT4H7:0 TCNT4H
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
The two Timer/Counter I/O locations (TCNT4H and TCNT4L, combined TCNT4) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying the
counter (TCNT4) while the counter is running introduces a risk of missing a compare
match between TCNT4 and one of the OCR4x Registers. Writing to the TCNT4
Register blocks (removes) the compare match on the following timer clock for all
compare units.
• Bit 7:0 – TCNT4H7:0 - Timer/Counter4 High Byte
18.11.35 TCNT4L – Timer/Counter4 Low Byte
Bit 7 6 5 4 3 2 1 0
NA ($A4) TCNT4L7:0 TCNT4L
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0