14 rx_ctrl - transceiver receive control register, Atmega128rfa1 – Rainbow Electronics ATmega128RFA1 User Manual
Page 111
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8266A-MCU Wireless-12/09
ATmega128RFA1
These bits define the received power threshold of the Energy above threshold
algorithm. The threshold is calculated by RSSI_BASE_VAL + 2CCA_ED_THRES
[dBm]. Any received power above this level is interpreted as a busy channel.
9.12.14 RX_CTRL – Transceiver Receive Control Register
Bit
7
6
5
4
NA ($14A)
Resx7
Resx6
Resx5
Resx4
RX_CTRL
Read/Write
RW
RW
RW
RW
Initial Value
1
0
1
1
Bit
3
2
1
0
NA ($14A)
PDT_THRES3
PDT_THRES2
PDT_THRES1
PDT_THRES0
RX_CTRL
Read/Write
RW
RW
RW
RW
Initial Value
0
1
1
1
The register controls the sensitivity of the Antenna Diversity Mode. Note that in High
Data Rate modes the ACR module will always be disabled.
•
Bit 7:4 – Resx7:4 - Reserved
•
Bit 3:0 – PDT_THRES3:0 - Receiver Sensitivity Control
These register bits control the sensitivity of the receiver correlation unit. If the Antenna
Diversity algorithm is enabled the value shall be set to PDT_THRES = 3. Otherwise it
shall be set back to the reset value. Values not listed in the following table are reserved.
Table 9-44 PDT_THRES Register Bits
Register Bits
Value
Description
0x7
Reset value, to be used if Antenna Diversity
algorithm is disabled
PDT_THRES3:0
0x3
Recommended correlator threshold for
Antenna Diversity operation
9.12.15 SFD_VALUE – Start of Frame Delimiter Value Register
Bit
7
6
5
4
3
2
1
0
NA ($14B)
SFD_VALUE7:0
SFD_VALUE
Read/Write
RW
RW
RW
RW
RW
RW
RW
RW
Initial Value
1
0
1
0
0
1
1
1
This register contains the one octet start-of-frame delimiter (SFD) to synchronize to a
received frame. The lower 4 bits must not be all zero to avoid decoding conflicts.
•
Bit 7:0 – SFD_VALUE7:0 - Start of Frame Delimiter Value
For compliant IEEE 802.15.4 networks set SFD_VALUE = 0xA7. This is the default
value of the register. To establish non IEEE 802.15.4 compliant networks the SFD value
can be changed to any other value. If enabled a RX_START interrupt is issued only if
the received SFD matches the register content of SFD_VALUE and a valid PHR is
received.