Rainbow Electronics ATmega128RFA1 - Manual (Page 285)

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8266A-MCU Wireless-12/09
ATmega128RFA1
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 5 – ICF3 - Timer/Counter3 Input Capture Flag
This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture
Register (ICR3) is set by the WGM33:0 to be used as the TOP value, the ICF3 Flag is
set when the counter reaches the TOP value. ICF3 is automatically cleared when the
Input Capture Interrupt Vector is executed. Alternatively, ICF3 can be cleared by writing
a logic one to its bit location.
• Bit 4 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 3 – OCF3C - Timer/Counter3 Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the
Output Compare Register C (OCR3C). Note that a Forced Output Compare (FOC3C)
strobe will not set the OCF3C Flag. OCF3C is automatically cleared when the Output
Compare Match C Interrupt Vector is executed. Alternatively, OCF3C can be cleared by
writing a logic one to its bit location.
• Bit 2 – OCF3B - Timer/Counter3 Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the
Output Compare Register B (OCR3B). Note that a Forced Output Compare (FOC3B)
strobe will not set the OCF3B Flag. OCF3B is automatically cleared when the Output
Compare Match B Interrupt Vector is executed. Alternatively, OCF3B can be cleared by
writing a logic one to its bit location.
• Bit 1 – OCF3A - Timer/Counter3 Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the
Output Compare Register A (OCR3A). Note that a Forced Output Compare (FOC3A)
strobe will not set the OCF3A Flag. OCF3A is automatically cleared when the Output
Compare Match A Interrupt Vector is executed. Alternatively, OCF3A can be cleared by
writing a logic one to its bit location.
• Bit 0 – TOV3 - Timer/Counter3 Overflow Flag
The setting of this flag is dependent of the WGM33:0 bits setting of the Timer/Counter3
Control Register. In Normal and CTC modes, the TOV3 Flag is set when the timer
overflows. TOV3 is automatically cleared when the Timer/Counter3 Overflow Interrupt
Vector is executed. Alternatively, TOV3 can be cleared by writing a logic one to its bit
location.
18.11.31 TCCR4A – Timer/Counter4 Control Register A
Bit 7 6 5 4 3 2 1 0
NA ($A0) COM4A1 COM4A0 COM4B1 COM4B0 COM4C1 COM4C0 WGM41 WGM40 TCCR4A
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
• Bit 7:6 – COM4A1:0 - Compare Output Mode for Channel A
The Timer/Counter4 has only limited functionality. Therefore the COM4A1:0 bits do not
control the output compare behavior of any pin. The following table shows the