Rainbow Electronics ATmega128RFA1 - Manual (Page 166)

166
8266A-MCU Wireless-12/09
ATmega128RFA1
register take effect in the regulator circuit. The write access from the software must be
aware of this process. Furthermore the value of LLDRH must be written first followed by
LLDRL. Otherwise the LLDRH write access will be ignored. The following Assembler
code fragment shows a working example. Note the polling of bit 3 LLCAL of the LLCR
register to verify the completion of the synchronization process.
Assembly Code Example
…
clr r20
IOST LLDRH,r18 ; write LLDRH first
IOST LLDRL,r19 ; write LLDRL second
IOST LLCR,r20 ; bit 0 cleared = disable automatic calibration
; poll LLCAL bit of LLCR to check if automatic calibration is
; turned of
wait_calib:
IOLD r20,LLCR
sbrc r20,3
rjmp wait_calib ; not executed if bit 3 of LLCR is cleared
…
12.6 Register Description
12.6.1 SMCR – Sleep Mode Control Register
Bit 7 6 5 4 3 2 1 0
$33 ($53) Res3 Res2 Res1 Res0 SM2 SM1 SM0 SE SMCR
Read/Write R R R R RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
The Sleep Mode Control Register contains control bits for power management.
• Bit 7:4 – Res3:0 - Reserved
• Bit 3:1 – SM2:0 - Sleep Mode Select bit 2
These bits select between the five available sleep modes. Standby modes are only
recommended for use with external crystals or resonators.
Table 12-4 SM Register Bits
Register Bits Value Description
0x00 Idle
0x01 ADC Noise Reduction (If Available)
0x02 Power Down
0x03 Power Save
0x04 Reserved
0x05 Reserved
0x06 Standby
SM2:0
0x07 Extended Standby
• Bit 0 – SE - Sleep Enable