Rainbow Electronics ATmega128RFA1 - Manual (Page 275)

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8266A-MCU Wireless-12/09
ATmega128RFA1
The corresponding Interrupt Vector is executed when the OCF1A Flag, located in
TIFR1, is set.
• Bit 0 – TOIE1 - Timer/Counter1 Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding
Interrupt Vector is executed when the TOV1 Flag, located in TIFR1, is set.
18.11.15 TIFR1 – Timer/Counter1 Interrupt Flag Register
Bit 7 6 5 4 3 2 1 0
$16 ($36) Res1 Res0 ICF1 Res OCF1C OCF1B OCF1A TOV1 TIFR1
Read/Write R R RW R RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 5 – ICF1 - Timer/Counter1 Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture
Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is
set when the counter reaches the TOP value. ICF1 is automatically cleared when the
Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing
a logic one to its bit location.
• Bit 4 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 3 – OCF1C - Timer/Counter1 Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the
Output Compare Register C (OCR1C). Note that a Forced Output Compare (FOC1C)
strobe will not set the OCF1C Flag. OCF1C is automatically cleared when the Output
Compare Match C Interrupt Vector is executed. Alternatively, OCF1C can be cleared by
writing a logic one to its bit location.
• Bit 2 – OCF1B - Timer/Counter1 Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the
Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B)
strobe will not set the OCF1B Flag. OCF1B is automatically cleared when the Output
Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by
writing a logic one to its bit location.
• Bit 1 – OCF1A - Timer/Counter1 Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the
Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A)
strobe will not set the OCF1A Flag. OCF1A is automatically cleared when the Output
Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by
writing a logic one to its bit location.
• Bit 0 – TOV1 - Timer/Counter1 Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting of the Timer/Counter1
Control Register. In Normal and CTC modes, the TOV1 Flag is set when the timer