Atmega128rfa1 – Rainbow Electronics ATmega128RFA1 User Manual
Page 290
290
8266A-MCU Wireless-12/09
ATmega128RFA1
The two Timer/Counter I/O locations (TCNT4H and TCNT4L, combined TCNT4) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying the
counter (TCNT4) while the counter is running introduces a risk of missing a compare
match between TCNT4 and one of the OCR4x Registers. Writing to the TCNT4
Register blocks (removes) the compare match on the following timer clock for all
compare units.
•
Bit 7:0 – TCNT4L7:0 - Timer/Counter4 Low Byte
18.11.36 OCR4AH – Timer/Counter4 Output Compare Register A High Byte
Bit
7
6
5
4
3
2
1
0
NA ($A9)
OCR4AH7:0
OCR4AH
Read/Write
RW
RW
RW
RW
RW
RW
RW
RW
Initial Value
0
0
0
0
0
0
0
0
The Output Compare Registers contain a 16-bit value that is continuously compared
with the counter value (TCNT4). A match can be used to generate an Output Compare
interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high
and low bytes are written simultaneously when the CPU writes to these registers, the
access is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16-
bit Registers" for details.
•
Bit 7:0 – OCR4AH7:0 - Timer/Counter4 Output Compare Register High Byte
18.11.37 OCR4AL – Timer/Counter4 Output Compare Register A Low Byte
Bit
7
6
5
4
3
2
1
0
NA ($A8)
OCR4AL7:0
OCR4AL
Read/Write
RW
RW
RW
RW
RW
RW
RW
RW
Initial Value
0
0
0
0
0
0
0
0
The Output Compare Registers contain a 16-bit value that is continuously compared
with the counter value (TCNT4). A match can be used to generate an Output Compare
interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high
and low bytes are written simultaneously when the CPU writes to these registers, the
access is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16-
bit Registers" for details.
•
Bit 7:0 – OCR4AL7:0 - Timer/Counter4 Output Compare Register Low Byte