Rainbow Electronics ATmega128RFA1 - Manual (Page 410)

410
8266A-MCU Wireless-12/09
ATmega128RFA1
27 ADC – Analog to Digital Converter
27.1 Features
• 10-bit Resolution
• Differential Non-Linearity is less than ± 0.5 LSB
• 2 LSB Integral Non-Linearity
• 3 - 240 µs Conversion Time
• Up to 330 kSPS (Up to 570 kSPS with 8-bit Resolution)
• 8 Multiplexed Single Ended Input Channels
• 11 Differential Input Channels
• 2 Differential Input Channels with an Optional Gain of 10x and 200x
• Internal Linear Temperature Sensor
• Optional Left Adjustment for ADC Result Readout
• 0 - V
AVDD
ADC Input Voltage Range
• 0 - V
EVDD
Differential ADC Input Voltage Range
• Selectable 1.5V, 1.6V or V
AVDD
ADC Reference Voltage
• Free Running or Single Conversion Mode
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceller
The ATmega128RFA1 features a 10-bit successive approximation ADC. The ADC is
connected to an 8-channel Analog Multiplexer which allows eight single-ended voltage
inputs constructed from the pins of Port F. The single-ended voltage inputs refer to 0V
(AVSS).
The device also supports multiple differential voltage input combinations. Two of the
differential inputs (ADC1 & ADC0 and ADC3 & ADC2) are equipped with a
programmable gain stage, providing amplification steps of 0 dB (1x), 20 dB (10x) or 46
dB (200x) on the differential input voltage before the A/D conversion. The differential
input channels are constructed of pairs out of the 8 single-ended inputs. They share a
common negative terminal (ADC0, ADC1 or ADC2), while most of the other ADC inputs
can be selected as the positive input terminal. If 1x or 10x gain is used, 8 bit resolution
can be expected. If 200x gain is used, 6 bit resolution can be expected.
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the
ADC is held at a constant level during conversion. A block diagram of the ADC is shown
in
Figure 27-1 on page 411 .
The analog components of the ADC are supplied from the analog supply voltage AVDD.
AVDD is generated from EVDD by an internal voltage generator. The logic part of the
ADC is supplied from the digital supply voltage DVDD. DVDD is generated from
DEVDD also by an internal voltage generator.
Internal reference voltages of nominally 1.5V, 1.6V or AVDD (1.8V) are provided on-
chip. The 1.6V reference is calibrated to ± 1 LSB during manufacturing. The reference
voltage can be monitored at the AREF pin. Additional de-coupling capacitance at AREF
is not required. A high capacitive loading of AREF will de-stabilize the internal reference
voltage generation. An external reference voltage in the range of 0 < V
AREF,EXT
≤ V
AVDD
may be used but must be supplied with a very low impedance.