Rainbow Electronics ATmega128RFA1 - Manual (Page 104)

104
8266A-MCU Wireless-12/09
ATmega128RFA1
Register Bits Value Description
0x1F STATE_TRANSITION_IN_PROGRESS
9.12.6 TRX_STATE – Transceiver State Control Register
Bit 7 6 5 4
NA ($142) TRAC_STATUS2 TRAC_STATUS1 TRAC_STATUS0 TRX_CMD4 TRX_STATE
Read/Write R R R RW
Initial Value 0 0 0 0
Bit 3 2 1 0
NA ($142) TRX_CMD3 TRX_CMD2 TRX_CMD1 TRX_CMD0 TRX_STATE
Read/Write RW RW RW RW
Initial Value 0 0 0 0
The states of the radio transceiver are controlled via register TRX_STATE using
register bits TRX_CMD. The read-only register bits TRAC_STATUS indicate the status
or result of an Extended Operating Mode transaction. A successful state transition shall
be confirmed by reading register bits TRX_STATUS. This register is used for both Basic
and Extended Operating Mode.
• Bit 7:5 – TRAC_STATUS2:0 - Transaction Status
The status of the RX_AACK and TX_ARET procedure is indicated by register bits
TRAC_STATUS. TRAC_STATUS is only valid in Extended Operating Modes. Details of
the algorithm and a description of the status information are given in the RX_AACK_ON
and TX_ARET_ON sections of the data-sheet. Even though the reset value for register
bits TRAC_STATUS is 0, the RX_AACK and TX_ARET procedures set the register bits
to TRAC_STATUS = 7 (INVALID) when it is started. Not all status values are used in
both
RX_AACK and TX_ARET transactions. In TX_ARET the status
SUCCESS_DATA_PENDING indicates a successful reception of an ACK frame with
frame pending bit set to 1. In RX_AACK the status SUCCESS_WAIT_FOR_ACK
indicates an ACK frame is about to sent in RX_AACK slotted acknowledgment. Slotted
acknowledgment operation must be enabled with the SLOTTED_OPERATION bit of
register XAH_CTRL_0. The application software must set the SLPTR bit of register
TRXPWR at the next back-off slot boundary in order to initiate a transmission of the
ACK frame. For details refer to IEEE 802.15.4-2006, chapter 5.5.4.1. Values not listed
in the following table are reserved.
Table 9-34 TRAC_STATUS Register Bits
Register Bits Value Description
0 SUCCESS (RX_AACK, TX_ARET)
1 SUCCESS_DATA_PENDING (TX_ARET)
2 SUCCESS_WAIT_FOR_ACK (RX_AACK)
3 CHANNEL_ACCESS_FAILURE (TX_ARET)
5 NO_ACK (TX_ARET)
TRAC_STATUS2:0
7 INVALID (RX_AACK, TX_ARET)
• Bit 4:0 – TRX_CMD4:0 - State Control Command