Rainbow Electronics ATmega128RFA1 - Manual (Page 431)

431
8266A-MCU Wireless-12/09
ATmega128RFA1
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. The AVDD supply voltage will also be enabled
if not already available. By writing it to zero, the ADC is turned off. Turning the ADC off
while a conversion is in progress will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free
Running mode, write this bit to one to start the first conversion. The first conversion
after ADSC has been written after the ADC has been enabled, or if ADSC is written at
the same time as the ADC is enabled, will include a start-up time to initialize the analog
blocks of the ADC. The start-up time is defined by the ADSUT bits of register ADCSRC.
ADSC will read as one as long as a conversion is in progress. When the conversion is
complete, it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will
start a conversion on a positive edge of the selected trigger signal. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an A/D conversion is completed and the Data Register are updated.
The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in
SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag.
Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be
disabled. This also applies if the SBI and CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion
Complete Interrupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the CPU frequency and the input clock
to the ADC.
Table 27-13. ADC Prescaler Selections
ADPS2 ADPS1 ADPS0 Division Factor
0 0 0 2
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 16
1 0 1 32
1 1 0 64
1 1 1 128
27.11.4 ADCSRC – ADC Control and Status Register C
Bit 7 6 5 4 3 2 1 0
NA ($77) ADTHT1 ADTHT0 Res0 ADSUT4 ADSUT3 ADSUT2 ADSUT1 ADSUT0 ADCSRC
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 1 0 1 0 1 0 0