Rainbow Electronics ATmega128RFA1 - Manual (Page 420)

420
8266A-MCU Wireless-12/09
ATmega128RFA1
disabled and enabled again for new reference selections. For internal references a
stable voltage is indicated by the REFOK bit in ADCSRB.
27.7 ADC Noise Canceller
The ADC features a noise canceller that enables conversion during sleep mode to
reduce noise induced from the CPU core and other I/O peripherals. The noise canceller
can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the
following procedure should be used:
1. Make sure that the ADC is enabled and is not busy converting. Single Conversion
mode must be selected and the ADC Conversion Complete interrupt must be
enabled.
2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion
once the CPU has been halted.
3. If no other interrupts occur before the A/D conversion completes, the ADC interrupt
will wake up the CPU and execute the ADC Conversion Complete interrupt routine.
If another interrupt wakes up the CPU before the A/D conversion is complete, that
interrupt will be executed, and an ADC Conversion Complete interrupt request will
be generated when the A/D conversion completes. The CPU will remain in active
mode until a new sleep command is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes
than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to
ADEN before entering such sleep modes to avoid excessive power consumption.
27.7.1 Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 27-11 on
page 421. An analog source applied to ADCn is subjected to the pin capacitance and
input leakage of that pin, regardless of whether that channel is selected as input for the
ADC. When the channel is selected, the source must drive the S/H capacitor through
the series resistance (combined resistance in the input path).
The ADC is optimized for analog signals having output impedance Z
OUT
of
approximately 3 kΩ or less. If such a source is used, the sampling time will be
negligible. If a source with higher impedance is used, the correct sampling time will
depend on how much time is needed to charge the S/H capacitor, which can vary
widely. The user is recommended to only use low impedance sources with slowly
varying signals, since this minimizes the required charge transfer to the S/H capacitor.
The required tracking time (input sampling switch closed) t
DTRCK
to settle to within 1 LSB
can be estimated to
ns k Z t
OUT DTRCK
097 . 0 ) 2000 / ( ⋅ + Ω =
for Z
OUT
> 3kΩ (worst case: maximum input step). A minimum tracking time of 500ns is
guaranteed by the conversion logic. Based on the ADC clock frequency the bits
ADTHT[1:0] of register ADCSRC allow the adjustment of the tracking time to the user’s
requirements.
Tracking time requirements should also be considered for the differential mode. The
input signal is sampled by the gain amplifier. The value of the input capacitance C
S/H
depends on the selected gain (~7pF for 200x gain, <1pF otherwise). The tracking is
equal to 50% of the clock period of CK
ADC2
. Hence in differential mode a slower clock
frequency is required for input sources with high impedance.