Rainbow Electronics ATmega128RFA1 - Manual (Page 314)

314
8266A-MCU Wireless-12/09
ATmega128RFA1
Figure 21-4. Fast PWM Mode, Timing Diagram
TCNTn
OCRnx Update and
TOVn Interrupt Flag Set
1 Period 2 3
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Interrupt Flag Set
4 5 6 7
The PWM frequency for the output can be calculated by the following equation:
256
/ _
⋅
=
N
f
f
O I clk
OCnxPWM
The N variable represents the pre-scale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating
a PWM waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM,
the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A
equal to MAX will result in a constantly high or low output (depending on the polarity of
the output set by the COM2A1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved
by setting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The
waveform generated will have a maximum frequency of f
oc2
= f
clk_I/O
/2 when OCR2A is
set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double
buffer feature of the Output Compare unit is enabled in the fast PWM mode.
21.5.4 Phase Correct PWM Mode
The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase
correct PWM waveform generation option. The phase correct PWM mode is based on a
dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then
from TOP to BOTTOM. TOP is defined as 0xFF when WGM22:0 = 1, and OCR2A when
WGM22:0 = 5. In non-inverting Compare Output mode, the Output Compare (OC2x) is
cleared on the compare match between TCNT2 and OCR2x while up-counting, and set
on the compare match while down-counting. In inverting Output Compare mode, the
operation is inverted. The dual-slope operation has lower maximum operation
frequency than single slope operation. However, due to the symmetric feature of the
dual-slope PWM modes, these modes are preferred for motor control applications.
In phase correct PWM mode the counter is incremented until the counter value matches
TOP. When the counter reaches TOP, it changes the count direction. The TCNT2 value
will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct
PWM mode is shown on
Figure 21-5 on page 315 . The TCNT2 value is in the timing
diagram shown as a histogram for illustrating the dual-slope operation. The diagram