Rainbow Electronics ATmega128RFA1 - Manual (Page 183)

183
8266A-MCU Wireless-12/09
ATmega128RFA1
13.5 Register Description
13.5.1 MCUSR – MCU Status Register
Bit 7 6 5 4 3 2 1 0
$34 ($54) Res2 Res1 Res0 JTRF WDRF BORF EXTRF PORF MCUSR
Read/Write R R R RW R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
The MCU Status Register provides information on which reset source caused an MCU
reset. To make use of the Reset Flags to identify a reset condition, the user should read
and then Reset the MCUSR as early as possible in the program. If the register is
cleared before another reset occurs, the source of the reset can be found by examining
the Reset Flags. Note, after power on the bit EXTRF has to be ignored.
• Bit 7:5 – Res2:0 - Reserved
• Bit 4 – JTRF - JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register
selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset,
or by writing a logic zero to the flag.
• Bit 3 – WDRF - Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 2 – BORF - Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 1 – EXTRF - External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 0 – PORF - Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to
the flag.
13.5.2 WDTCSR – Watchdog Timer Control Register
Bit 7 6 5 4 3 2 1 0
NA ($60) WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCSR
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – WDIF - Watchdog Timeout Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer
is configured for interrupt. WDIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic
one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out
Interrupt is executed.