Rainbow Electronics ATmega128RFA1 - Manual (Page 330)

330
8266A-MCU Wireless-12/09
ATmega128RFA1
22 SPI- Serial Peripheral Interface
22.1 Features
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer
between the ATmega128RFA1 and peripheral devices or between several AVR
devices.
The ATmega128RFA1 SPI includes the following features:
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
22.2 Functional Description
USART can also be used in Master SPI mode, see "USART in SPI Mode" on page 368 .
The Power Reduction SPI bit, PRSPI, in "PRR0 – Power Reduction Register0" on page
167 must be written to zero to enable SPI module. The block diagram of the SPI
interface is shown in Figure 22-1 on page 331 .
The interconnection between Master and Slave CPUs with SPI is shown in Figure 22-2
on page 331 . The system consists of two shift Registers, and a Master clock generator.
The SPI Master initiates the communication cycle when pulling low the Slave Select SS
__
pin of the desired Slave. Master and Slave prepare the data to be sent in their
respective shift Registers, and the Master generates the required clock pulses on the
SCK line to interchange data. Data is always shifted from Master to Slave on the Master
Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out,
MISO, line. After each data packet, the Master will synchronize the Slave by pulling
high the Slave Select, SS
__
, line.
When configured as a Master, the SPI interface has no automatic control of the SS
__
line.
This must be handled by user software before communication can start. When this is
done, writing a byte to the SPI Data Register starts the SPI clock generator, and the
hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock
generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable
bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may
continue to shift the next byte by writing it into SPDR, or signal the end of packet by
pulling high the Slave Select, SS
__
line. The last incoming byte will be kept in the Buffer
Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated
as long as the SS __
pin is driven high. In this state, software may update the contents of
the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock
pulses on the SCK pin until the SS pin is driven low. As one byte has been completely
shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE,
in the SPCR Register is set, an interrupt is requested. The Slave may continue to place
new data to be sent into SPDR before reading the incoming data. The last incoming
byte will be kept in the Buffer Register for later use.