Rainbow Electronics ATmega128RFA1 - Manual (Page 243)

243
8266A-MCU Wireless-12/09
ATmega128RFA1
17.9.8 TIFR0 – Timer/Counter0 Interrupt Flag Register
Bit 7 6 5 4 3 2 1 0
$15 ($35) Res4 Res3 Res2 Res1 Res0 OCF0B OCF0A TOV0 TIFR0
Read/Write R R R R R RW RW RW
Initial Value 0 0 0 0 0 0 0 0
• Bit 7:3 – Res4:0 - Reserved
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 2 – OCF0B - Timer/Counter0 Output Compare B Match Flag
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter0 and
the data in OCR0B Output Compare Register. OCF0B is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared
by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter
Compare B Match Interrupt Enable) and OCF0B are set, the Timer/Counter Compare
Match Interrupt is executed.
• Bit 1 – OCF0A - Timer/Counter0 Output Compare A Match Flag
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and
the data in OCR0A Output Compare Register. OCF0A is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared
by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter
Compare A Match Interrupt Enable) and OCF0A are set, the Timer/Counter Compare
Match Interrupt is executed.
• Bit 0 – TOV0 - Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0
(Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set, the Timer/Counter0
Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit
setting.