Rainbow Electronics ATmega128RFA1 - Manual (Page 418)

418
8266A-MCU Wireless-12/09
ATmega128RFA1
the MUX4:0 bits need to be modified then a write access to the MUX4:0 bits is
sufficient.
27.6.2 ADC Input Channels
The ADC input channels can be changed while the ADC is running under the condition
that the previous channel was a single-ended one. Changing between differential
channels however requires that the ADC is disabled and enabled again to make the
ADC go through the initial start-up phase.
If changing from single-ended to single-ended or from single-ended to differential input
channels a settling phase is automatically inserted by the ADC interface logic after the
input channel is modified. The settling phase is required by the ADC and the gain
amplifier to stabilize. If a conversions start is requested during this settling phase, by
setting ADSC or by a trigger event in Auto Triggered mode then the conversion is
started only after the settling phase has completed.
In case the MUXn bits are altered during an ongoing conversion, the ADC input channel
is changed after the conversion has completed. MUXn changes occurring during the
tracking phase, which follows a conversion, will stop the tracking phase and the ADC
settling phase will be entered.
In Free Running mode MUXn can also be modified. In this case the ADC input channel
is changed after the conversion end or from the subsequent tracking phase. As a
consequence the time from one conversion to the next is extended by the duration of
the ADC settling phase.
The ADC settling time t
ASET
depends on the previous and the new channel and on the
configuration of the ADSUT4:0 and ADTHT1:0 bits as shown in Table 27-6 below .
Additionally a synchronization delay t
CHDLY
from 2 CPU to 2 ADC Clock cycles is
required between changing the ADC input channel selection and the beginning of the
settling phase. For details see the timing diagrams
Figure 27-9 on page 419 and Figure
27-10 on page 419.
If the analog input signal encounters large variations it can be useful to manually reset
the ADC and the gain amplifier before starting a new conversion. To achieve this, the
settling phase can be forced without modifying MUXn by writing a logic one to the
Analog Channel Change bit ACCH in ADCSRB. Using the ACCH bit is only
recommended for single-ended input channels. For differential input channels the ADC
and the gain amplifier can be reset if the ADC is disabled and enabled again.
Table 27-6. Settling Time after Channel Changes
Channel Transition Settling Time t
ASET
in ADC Clock Cycles
Single-Ended or Differential to Single-Ended ADTHT+2
Single-Ended to Differential 4(ADSUT+1) + 2(ADTHT+2)
Differential to Differential Requires the ADC to be disabled and enabled
again.