Rainbow Electronics ATmega128RFA1 - Manual (Page 279)

279
8266A-MCU Wireless-12/09
ATmega128RFA1
Register Bits Value Description
0x7 Fast PWM, 10-bit
0x8 PWM, Phase and frequency correct, TOP =
ICRn
0x9 PWM, Phase and frequency correct, TOP =
OCRnA
0xA PWM, Phase correct, TOP = ICRn
0xB PWM, Phase correct, TOP = OCRnA
0xC CTC, TOP = OCRnA
0xD Reserved
0xE Fast PWM, TOP = ICRn
0xF Fast PWM, TOP = OCRnA
• Bit 2:0 – CS32:30 - Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter3
according to the following table. If external pin modes are used for the Timer/Counter3,
transitions on the T3 pin will clock the counter even if the pin is configured as an output.
This feature allows software control of the counting.
Table 18-17 CS3 Register Bits
Register Bits Value Description
0x00 No clock source (Timer/Counter stopped)
0x01 clk_IO/1 (no prescaling)
0x02 clk_IO/8 (from prescaler)
0x03 clk_IO/64 (from prescaler)
0x04 clk_IO/256 (from prescaler)
0x05 clk_IO/1024 (from prescaler)
0x06 External clock source on Tn pin, clock on
falling edge
CS32:30
0x07 External clock source on Tn pin, clock on
rising edge
18.11.18 TCCR3C – Timer/Counter3 Control Register C
Bit 7 6 5 4 3 2 1 0
NA ($92) FOC3A FOC3B FOC3C Res4 Res3 Res2 Res1 Res0 TCCR3C
Read/Write RW RW RW R R R R R
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – FOC3A - Force Output Compare for Channel A
The FOC3A bit is only active when the WGM33:0 bits specify a non-PWM mode. When
writing a logical one to the FOC3A bit, an immediate compare match is forced on the
waveform generation unit. The OC3A output is changed according to its COM3A1:0 bits
setting. Note that the FOC3A bits are implemented as strobes. Therefore it is the value
present in the COM3A1:0 bits that determine the effect of the forced compare. A
FOC3A strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR3A as TOP. The FOC3A bits are always read
as zero.