Rainbow Electronics ATmega128RFA1 - Manual (Page 375)

375
8266A-MCU Wireless-12/09
ATmega128RFA1
When set to one the LSB of the data word is transmitted first. When set to zero the
MSB of the data word is transmitted first. Refer to section "Frame Formats" for details.
• Bit 1 – UCPHA0 - Clock Phase
The UCPHA0 bit setting determines if data is sampled on the leading (first) or tailing
(last) edge of XCK0. Refer to the section "SPI Data Modes and Timing" for details.
• Bit 0 – UCPOL0 - Clock Polarity
The UCPOL0 bit sets the polarity of the XCK0 clock. The combination of the UCPOL0
and UCPHA0 bit settings determine the timing of the data transfer. Refer to the section
"SPI Data Modes and Timing" for details.
24.6.6 UCSR1A – USART1 MSPIM Control and Status Register A
Bit 7 6 5 4 3 2 1 0
NA ($C8) RXC1 TXC1 UDRE1 UCSR1A
Read/Write R RW R
Initial Value 0 0 0
• Bit 7 – RXC1 - USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when
the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is
disabled, the receive buffer will be flushed and consequently the RXC1 bit will become
zero. The RXC1 Flag can be used to generate a Receive Complete interrupt (see
description of the RXCIE1 bit).
• Bit 6 – TXC1 - USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted
out and there are no new data currently present in the transmit buffer (UDR1). The
TXC1 Flag bit is automatically cleared when a transmit complete interrupt is executed,
or it can be cleared by writing a one to its bit location. The TXC1 Flag can generate a
Transmit Complete interrupt (see description of the TXCIE1 bit).
• Bit 5 – UDRE1 - USART Data Register Empty
The UDRE1 Flag indicates if the transmit buffer (UDR1) is ready to receive new data. If
UDRE1 is one, the buffer is empty, and therefore ready to be written. The UDRE1 Flag
can generate a Data Register Empty interrupt (see description of the UDRIE1 bit).
UDRE1 is set after a reset to indicate that the Transmitter is ready.
24.6.7 UCSR1B – USART1 MSPIM Control and Status Register B
Bit 7 6 5 4 3 2 1 0
NA ($C9) RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSR1B
Read/Write RW RW RW RW RW
Initial Value 0 0 1 0 0
• Bit 7 – RXCIE1 - RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC1 Flag. A USART Receive Complete
interrupt will be generated only if the RXCIE1 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the RXC1 bit in UCSR1A is set.