Rainbow Electronics ATmega128RFA1 - Manual (Page 322)

322
8266A-MCU Wireless-12/09
ATmega128RFA1
advanced by at least one before the processor can read the counter value. After
wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and
resumes execution from the instruction following SLEEP.
• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an
incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading
TCNT2 must be done through a register synchronized to the internal I/O clock
domain. Synchronization takes place for every rising TOSC1 edge. When waking up
from Powersave mode, and the I/O clock (clk
I/O
) again becomes active, TCNT2 will
read as the previous value (before entering sleep) until the next rising TOSC1 edge.
The phase of the TOSC clock after waking up from Power-save mode is essentially
unpredictable, as it depends on the wake-up time. The recommended procedure for
reading TCNT2 is thus as follows:
1. Write any value to either of the registers OCR2x or TCCR2x.
2. Wait for the corresponding Update Busy Flag to be cleared.
3. Read TCNT2.
• During asynchronous operation, the synchronization of the Interrupt Flags for the
asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is
therefore advanced by at least one before the processor can read the timer value
causing the setting of the Interrupt Flag. The Output Compare pin is changed on the
timer clock and is not synchronized to the processor clock.
• If the CPU wakes up from asynchronous timer and goes back to sleep again, it may
wakeup multiple times or the IRQ is called multiple times. This may be avoided if the
CPU waits with the next sleep instruction until the next asynchronous clock arrives.
21.10 Timer/Counter Prescaler
Figure 21-12. Prescaler for Timer/Counter2
10-BI T T/C PRES CA LER
TIMER/ COUNTER2 CLOCK SOURCE
clk
I/O
clk
T2S
TOSC1
AS2
CS20
CS21
CS22
cl
k T
2
S
/8
cl
k T
2
S
/6
4
cl
k T
2
S
/1
2
8
cl
k T
2
S
/1
02
4
cl
k T
2
S
/2
5
6
cl
k T
2
S
/3
2
0
PS RASY
Clear
clk
T2
AMR
EXCLKAMR
The register ASSR defines the clock source for the asynchronous Timer/Counter2. The
clock source for Timer/Counter2 is named clk
T2S
. clk
T2S
is by default connected to the
main system I/O clock clk
IO
. By setting the AS2 bit in ASSR, Timer/Counter2 is
asynchronously clocked either from the TOSC1 or from the AMR pin. This enables the
use of Timer/Counter2 as a Real Time Counter (RTC).