Rainbow Electronics ATmega128RFA1 - Manual (Page 259)

259
8266A-MCU Wireless-12/09
ATmega128RFA1
OCnx is set at BOTTOM. In inverting Compare Output mode output is set on compare
match and cleared at BOTTOM. Due to the single-slope operation, the operating
frequency of the fast PWM mode can be twice as high as the phase-correct and phase
and frequency correct PWM modes that use dual-slope operation. This high frequency
makes the fast PWM mode well suited for power regulation, rectification and DAC
applications. High frequency allows physically small sized external components (coils,
capacitors), hence reducing total system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either
ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to
0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM
resolution R
FPWM
in bits can be calculated with the following equation:
) 2 log(
) 1 log( +
=
TOP
R
FPWM
In fast PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF or 0x03FF (WGMn3:0 = 5, 6 or 7), the value in
ICRn (WGMn3:0 = 14) or the value in OCRnA (WGMn3:0 = 15). The counter is then
cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is
shown in Figure 18-7. The figure shows fast PWM mode when OCRnA or ICRn is used
to define TOP. The TCNTn value is in the timing diagram shown as a histogram for
illustrating the single-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare
matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a
compare match occurs.
Figure 18-7. Fast PWM Mode Timing Diagram
TCNTn
OCRnx / TOP Update
and TOVn Interrupt Flag
Set and OCnA Interrupt
Flag Set or ICFn
Interrupt Flag Set
(Interrupt on TOP)
1 7 Period 2 3 4 5 6 8
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In
addition the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set
when either OCRnA or ICRn is used to define the TOP value. If one of the interrupts are
enabled, the interrupt handler routine can be utilized for updating the TOP and compare
values.
When changing the TOP value the program must ensure that the new TOP value is
higher or equal to the value of all of the Compare Registers. A compare match will
never occur between the TCNTn and the OCRnx if the TOP value is lower than any of
the Compare Registers. Note that when working with fixed TOP values the unused bits
are masked to zero when any of the OCRnx Registers are written.