Rainbow Electronics ATmega128RFA1 - Manual (Page 280)

280
8266A-MCU Wireless-12/09
ATmega128RFA1
• Bit 6 – FOC3B - Force Output Compare for Channel B
The FOC3B bit is only active when the WGM33:0 bits specify a non-PWM mode. When
writing a logical one to the FOC3B bit, an immediate compare match is forced on the
waveform generation unit. The OC3B output is changed according to its COM3B1:0 bits
setting. Note that the FOC3B bits are implemented as strobes. Therefore it is the value
present in the COM3B1:0 bits that determine the effect of the forced compare. A
FOC3B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR1B as TOP. The FOC3B bits are always read
as zero.
• Bit 5 – FOC3C - Force Output Compare for Channel C
The FOC3C bit is only active when the WGM33:0 bits specify a non-PWM mode. When
writing a logical one to the FOC3C bit, an immediate compare match is forced on the
waveform generation unit. The OC3C output is changed according to its COM3C1:0 bits
setting. Note that the FOC3C bits are implemented as strobes. Therefore it is the value
present in the COM3C1:0 bits that determine the effect of the forced compare. A
FOC3C strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR3C as TOP. The FOC3C bits are always read
as zero.
• Bit 4:0 – Res4:0 - Reserved
These bits are reserved for future use.
18.11.19 TCNT3H – Timer/Counter3 High Byte
Bit 7 6 5 4 3 2 1 0
NA ($95) TCNT3H7:0 TCNT3H
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
The two Timer/Counter I/O locations (TCNT3H and TCNT3L, combined TCNT3) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying the
counter (TCNT3) while the counter is running introduces a risk of missing a compare
match between TCNT3 and one of the OCR3x Registers. Writing to the TCNT3
Register blocks (removes) the compare match on the following timer clock for all
compare units.
• Bit 7:0 – TCNT3H7:0 - Timer/Counter3 High Byte
18.11.20 TCNT3L – Timer/Counter3 Low Byte
Bit 7 6 5 4 3 2 1 0
NA ($94) TCNT3L7:0 TCNT3L
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0