Rainbow Electronics ATmega128RFA1 - Manual (Page 376)

376
8266A-MCU Wireless-12/09
ATmega128RFA1
• Bit 6 – TXCIE1 - TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC1 Flag. A USART Transmit Complete
interrupt will be generated only if the TXCIE1 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the TXC1 bit in UCSR1A is set.
• Bit 5 – UDRIE1 - USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDRE1 Flag. A Data Register Empty
interrupt will be generated only if the UDRIE1 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the UDRE1 bit in UCSR1A is set.
• Bit 4 – RXEN1 - Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will
override normal port operation for the RxD1 pin when enabled. Disabling the Receiver
will flush the receive buffer. Only enabling the receiver in MSPI mode (i.e. setting
RXEN1=1 and TXEN1=0) has no meaning since it is the transmitter that controls the
transfer clock and since only master mode is supported.
• Bit 3 – TXEN1 - Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override
normal port operation for the TxD1 pin when enabled. The disabling of the Transmitter
(writing TXEN1 to zero) will not become effective until ongoing and pending
transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer
Register do not contain data to be transmitted. When disabled, the Transmitter will no
longer override the TxD1 port.
24.6.8 UCSR1C – USART1 MSPIM Control and Status Register C
Bit 7 6 5 4 3 2 1 0
NA ($CA) UDORD1 UCPHA1 UCPOL1 UCSR1C
Read/Write RW RW RW
Initial Value 1 1 0
• Bit 2 – UDORD1 - Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the
MSB of the data word is transmitted first. Refer to section "Frame Formats" for details.
• Bit 1 – UCPHA1 - Clock Phase
The UCPHA1 bit setting determines if data is sampled on the leading (first) or tailing
(last) edge of XCK1. Refer to the section "SPI Data Modes and Timing" for details.
• Bit 0 – UCPOL1 - Clock Polarity
The UCPOL1 bit sets the polarity of the XCK1 clock. The combination of the UCPOL1
and UCPHA1 bit settings determine the timing of the data transfer. Refer to the section
"SPI Data Modes and Timing" for details.