Rainbow Electronics ATmega128RFA1 - Manual (Page 228)

228
8266A-MCU Wireless-12/09
ATmega128RFA1
Figure 17-2. Counter Unit Block Diagram
DATA BUS
TCNTn Control Logic
count
TOVn
(Int.Req.)
Clock Select
top
Tn
Edge
Detector
( From Prescaler )
clk
Tn
bottom
direction
clear
Signal description (internal signals):
count Increment or decrement TCNT0 by 1;
direction Select between increment and decrement;
clear Clear TCNT0 (set all bits to zero);
clk
Tn
Timer/Counter clock referred to as clk
T0
in the following text;
top Signalize that TCNT0 has reached maximum value;
bottom Signalize that TCNT0 has reached minimum value (zero);
Depending of the mode of operation used, the counter is cleared, incremented or
decremented at each timer clock (clk
T0
). clk
T0
can be generated from an external or
internal clock source selected by the Clock Select bits (CS02:0). When no clock source
is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be
accessed by the CPU regardless of whether clk
T0
is present or not. A CPU write access
overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits
located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in
the Timer/Counter Control Register B (TCCR0B). There are close connections between
how the counter behaves (counts) and how waveforms are generated on the Output
Compare outputs OC0A and OC0B. For more details about advanced counting
sequences and waveform generation, see
"Modes of Operation" on page 232 .
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation
selected by the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.
17.5 Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare
Registers (OCR0A and OCR0B). The comparator signals a match whenever TCNT0
equals OCR0A or OCR0B. A match will set the Output Compare Flag (OCF0A or
OCF0B) at the next clock cycle of the timer. If the corresponding interrupt is enabled,
the Output Compare Flag generates an Output Compare interrupt. The Output
Compare Flag is automatically cleared when the interrupt is executed. The flag can
alternatively be software-cleared by writing a logical one to its I/O bit location. The
Waveform Generator uses the match signal to generate an output according to the
operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits.
The MAX and BOTTOM signals are used by the Waveform Generator for handling the
special cases of the extreme values in some modes of operation (refer to
"Modes of
Operation" on page 232 ).