Rainbow Electronics ATmega128RFA1 - Manual (Page 405)

405
8266A-MCU Wireless-12/09
ATmega128RFA1
Register Bits Value Description
0x01 4
0x02 16
0x03 64
25.9.4 TWDR – TWI Data Register
Bit 7 6 5 4 3 2 1 0
NA ($BB) TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 TWDR
Read/Write RW RW RW RW RW RW RW RW
Initial Value 1 1 1 1 1 1 1 1
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode,
the TWDR contains the last byte received. It is writable while the TWI is not in the
process of shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by
hardware. Note that the Data Register cannot be initialized by the user before the first
interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data
is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the
last byte present on the bus, except after a wake up from a sleep mode by the TWI
interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus
arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit
is automatically controlled by the TWI logic. The CPU cannot access the ACK bit
directly.
• Bit 7:0 – TWD7:0 - TWI Data Register Byte
25.9.5 TWAR – TWI (Slave) Address Register
Bit 7 6 5 4 3 2 1 0
NA ($BA) TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE TWAR
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant
bits of TWAR) to which the TWI will respond when programmed as a Slave Transmitter
or Receiver. This register is not needed in the Master modes. In multi-master systems
TWAR must be set in Masters which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable the recognition of the general call address (0x00).
There is an associated address comparator that looks for the slave address (or general
call address if enabled) in the received serial address. If a match is found, an interrupt
request is generated.
• Bit 7:1 – TWA6:0 - TWI (Slave) Address
These bits contain the TWI address operated as a Slave device.
• Bit 0 – TWGCE - TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.