28 jtag interface and on-chip debug system, 1 features, 2 overview – Rainbow Electronics ATmega128RFA1 User Manual
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8266A-MCU Wireless-12/09
ATmega128RFA1
28 JTAG Interface and On-chip Debug System
28.1 Features
•
JTAG (IEEE std. 1149.1 Compliant) Interface
•
Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG)
Standard
•
Debugger Access to:
o
All Internal Peripheral Units
o
Internal and External RAM
o
The Internal Register File–Program Counter
o
EEPROM and Flash Memories
•
Extensive on-chip debug Support for Break Conditions, Including
o
AVR Break Instruction
o
Break on Change of Program Memory Flow
o
Single Step Break
o
Program Memory Breakpoints on Single Address or Address Range
o
Data Memory Breakpoints on Single Address or Address Range
•
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG
Interface
•
On-chip debugging Supported by AVR Studio
®
28.2 Overview
The AVR IEEE std. 1149.1 compliant JTAG interface can be used for
•
Testing PCBs by using the JTAG Boundary-scan capability
•
Programming the non-volatile memories, Fuses and Lock bits
•
On-chip debugging
A brief description is given in the following sections. Detailed descriptions for
Programming via the JTAG interface, and using the Boundary-scan Chain can be found
in the sections
"Programming via the JTAG Interface" on page 481
via the JTAG Interface" on page 481
, respectively. The on-chip debug support is
considered being private JTAG instructions, and distributed within ATMEL and to
selected third party vendors only.
shows a block diagram of the JTAG interface and the on-chip
debug system. The TAP Controller is a state machine controlled by the TCK and TMS
signals. The TAP Controller selects either the JTAG Instruction Register or one of
several Data Registers as the scan chain (Shift Register) between the TDI – input and
TDO – output. The Instruction Register holds JTAG instructions controlling the behavior
of a Data Register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data
Registers used for board-level testing. The JTAG Programming Interface (actually
consisting of several physical and virtual Data Registers) is used for serial programming
via the JTAG interface. The internal scan-chain and breakpoint scan-chain are used for
on-chip debugging only.