Rainbow Electronics ATmega128RFA1 - Manual (Page 362)

362
8266A-MCU Wireless-12/09
ATmega128RFA1
This bit is set if the next character in the receive buffer had a Parity Error when received
and the Parity Checking was enabled at that point (UPM11 = 1). This bit is valid until the
receive buffer (UDR1) is read. Always set this bit to zero when writing to UCSR1A.
• Bit 1 – U2X1 - Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using
synchronous operation. Writing this bit to one will reduce the divisor of the baud rate
divider from 16 to 8 effectively doubling the transfer rate for asynchronous
communication.
• Bit 0 – MPCM1 - Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCM1 bit is
written to one, all the incoming frames received by the USART Receiver that do not
contain address information will be ignored. The Transmitter is unaffected by the
MPCM1 setting. For more detailed information see section "Multi-processor
Communication Mode".
23.10.9 UCSR1B – USART1 Control and Status Register B
Bit 7 6 5 4 3 2 1 0
NA ($C9) RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 UCSR1B
Read/Write RW RW RW RW RW RW R W
Initial Value 0 0 1 0 0 0 0 0
• Bit 7 – RXCIE1 - RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC1 Flag. A USART Receive Complete
interrupt will be generated only if the RXCIE1 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the RXC1 bit in UCSR1A is set.
• Bit 6 – TXCIE1 - TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC1 Flag. A USART Transmit Complete
interrupt will be generated only if the TXCIE1 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the TXC1 bit in UCSR1A is set.
• Bit 5 – UDRIE1 - USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDRE1 Flag. A Data Register Empty
interrupt will be generated only if the UDRIE1 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the UDRE1 bit in UCSR1A is set.
• Bit 4 – RXEN1 - Receiver Enable
Writing this bit to one enables the USART Receiver. The Receiver will override normal
port operation for the RxD1 pin when enabled. Disabling the Receiver will flush the
receive buffer invalidating the FE1, DOR1 and UPE1 Flags.
• Bit 3 – TXEN1 - Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override
normal port operation for the TxD1 pin when enabled. The disabling of the Transmitter
(writing TXEN1 to zero) will not become effective until ongoing and pending
transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer
Register do not contain data to be transmitted. When disabled, the Transmitter will no
longer override the TxD1 port.
• Bit 2 – UCSZ12 - Character Size